net/vmxnet3/vmxnet3_defs.h

35 	VMXNET3_REG_VRRS	= 0x0,	/* Vmxnet3 Revision Report Selection */
36 	VMXNET3_REG_UVRS	= 0x8,	/* UPT Version Report Selection */
37 	VMXNET3_REG_DSAL	= 0x10,	/* Driver Shared Address Low */
38 	VMXNET3_REG_DSAH	= 0x18,	/* Driver Shared Address High */
39 	VMXNET3_REG_CMD		= 0x20,	/* Command */
40 	VMXNET3_REG_MACL	= 0x28,	/* MAC Address Low */
41 	VMXNET3_REG_MACH	= 0x30,	/* MAC Address High */
42 	VMXNET3_REG_ICR		= 0x38,	/* Interrupt Cause Register */
43 	VMXNET3_REG_ECR		= 0x40	/* Event Cause Register */
46 /* BAR 0 */
48 	VMXNET3_REG_IMR		= 0x0,	 /* Interrupt Mask Register */
49 	VMXNET3_REG_TXPROD	= 0x600, /* Tx Producer Index */
50 	VMXNET3_REG_RXPROD	= 0x800, /* Rx Producer Index for ring 1 */
51 	VMXNET3_REG_RXPROD2	= 0xA00	 /* Rx Producer Index for ring 2 */
54 #define VMXNET3_PT_REG_SIZE     4096	/* BAR 0 */
58 #define VMXNET3_REG_ALIGN_MASK  0x7
61 #define VMXNET3_IO_TYPE_PT              0
63 #define VMXNET3_IO_ADDR(type, reg)      (((type) << 24) | ((reg) & 0xFFFFFF))
65 #define VMXNET3_IO_REG(addr)            ((addr) & 0xFFFFFF)
68 	VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
87 	VMXNET3_CMD_FIRST_GET = 0xF00D0000,
105  *	Byte 0 :	7.....len.....0
107  *	Byte 2 : 	5.msscof.0 ext1  dtype
111  *	Byte 0:		13...msscof...6
112  *	Byte 1 : 	5.msscof.0 ext1  dtype
114  *	Byte 3 :	7.....len.....0
160 #define VMXNET3_OM_NONE         0
187 #define VMXNET3_TCD_TXIDX_SHIFT	0
223 #define VMXNET3_RXD_BTYPE_HEAD   0    /* head only */
345 	VMXNET3_RCD_RSS_TYPE_NONE     = 0,
379 /* Minimum size of a type 0 buffer */
414  VMXNET3_ERR_NOEOP        = 0x80000000,  /* cannot find the EOP desc of a pkt */
415  VMXNET3_ERR_TXD_REUSE    = 0x80000001,  /* reuse TxDesc before tx completion */
416  VMXNET3_ERR_BIG_PKT      = 0x80000002,  /* too many TxDesc for a pkt */
417  VMXNET3_ERR_DESC_NOT_SPT = 0x80000003,  /* descriptor type not supported */
418  VMXNET3_ERR_SMALL_BUF    = 0x80000004,  /* type 0 buffer too small */
419  VMXNET3_ERR_STRESS       = 0x80000005,  /* stress option firing in vmkernel */
420  VMXNET3_ERR_SWITCH       = 0x80000006,  /* mode switch failure */
421  VMXNET3_ERR_TXD_INVALID  = 0x80000007,  /* invalid TxDesc */
425 #define VMXNET3_CDTYPE_TXCOMP      0    /* Tx Completion Descriptor */
430 	VMXNET3_GOS_BITS_UNK    = 0,   /* unknown */
519 	VMXNET3_IMM_AUTO   = 0,
525 	VMXNET3_IT_AUTO = 0,
537 #define VMXNET3_IC_DISABLE_ALL  0x1   /* bit 0 */
575 	VMXNET3_RXM_UCAST     = 0x01,  /* unicast only */
576 	VMXNET3_RXM_MCAST     = 0x02,  /* multicast passing the filters */
577 	VMXNET3_RXM_BCAST     = 0x04,  /* broadcast only */
578 	VMXNET3_RXM_ALL_MULTI = 0x08,  /* all multicast */
579 	VMXNET3_RXM_PROMISC   = 0x10  /* promiscuous */
595 #define VMXNET3_PM_WAKEUP_MAGIC       cpu_to_le16(0x01)  /* wake up on magic pkts */
596 #define VMXNET3_PM_WAKEUP_FILTER      cpu_to_le16(0x02)  /* wake up on pkts matching
653 	VMXNET3_COALESCE_DISABLED   = 0,
694 	VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
695 	VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
696 	VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
697 	VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
698 	VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
699 	VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
740 #define VMXNET3_ECR_RQERR       (1 << 0)
747 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
754 			(idx) = 0;\
756 	} while (0)
764 	((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
770 #define VMXNET3_LINK_DOWN       0