21 #define DP83867_DEVADDR		0x1f  macro
188 	val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);  in dp83867_set_wol()
202 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,  in dp83867_set_wol()
204 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,  in dp83867_set_wol()
206 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,  in dp83867_set_wol()
215 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,  in dp83867_set_wol()
217 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,  in dp83867_set_wol()
219 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,  in dp83867_set_wol()
241 	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);  in dp83867_set_wol()
256 	value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);  in dp83867_get_wol()
268 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
273 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
278 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
440 		phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
443 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
456 		const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_verify_rgmii_cfg()
625 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_init()
628 	bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);  in dp83867_config_init()
634 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
678 		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);  in dp83867_config_init()
693 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);  in dp83867_config_init()
705 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);  in dp83867_config_init()
714 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,  in dp83867_config_init()
720 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()
731 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
742 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
750 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);  in dp83867_config_init()
759 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);  in dp83867_config_init()
766 			phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_init()
793 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()