24 #define DP83822_DEVADDR		0x1f  macro
153 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,  in dp83822_set_wol()
155 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,  in dp83822_set_wol()
157 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,  in dp83822_set_wol()
160 		value = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
168 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
171 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
174 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
188 		return phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
191 		return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
205 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_get_wol()
211 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
216 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
221 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
305 	return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,  in dp8382x_disable_wol()
382 			err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_config_init()
437 			err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_config_init()
495 	val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);  in dp83822_read_straps()
542 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_suspend()
556 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_resume()
558 	phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |  in dp83822_resume()