Lines Matching refs:MII_BCM7XXX_TEST
25 #define MII_BCM7XXX_TEST 0x1f macro
260 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_01_afe_config_init()
292 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
331 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_eee_enable()
377 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
456 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_read_mmd()
470 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_read_mmd()
486 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_write_mmd()
501 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_write_mmd()
526 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_config_init()
541 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
558 { MII_BCM7XXX_TEST, 0x008b }, in bcm7xxx_suspend()
561 { MII_BCM7XXX_TEST, 0x000f }, in bcm7xxx_suspend()
563 { MII_BCM7XXX_TEST, 0x000b }, in bcm7xxx_suspend()