Lines Matching full:phydev
51 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_d0_afe_config_init() argument
54 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
57 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
60 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
63 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
66 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
69 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
72 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
77 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
83 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_d0_afe_config_init()
86 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_d0_afe_config_init()
91 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_e0_plus_afe_config_init() argument
94 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_e0_plus_afe_config_init()
97 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_e0_plus_afe_config_init()
100 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_e0_plus_afe_config_init()
105 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_e0_plus_afe_config_init()
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
111 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_e0_plus_afe_config_init()
114 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_e0_plus_afe_config_init()
119 static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_a0_patch_afe_config_init() argument
122 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003); in bcm7xxx_28nm_a0_patch_afe_config_init()
125 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b); in bcm7xxx_28nm_a0_patch_afe_config_init()
128 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3); in bcm7xxx_28nm_a0_patch_afe_config_init()
131 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6); in bcm7xxx_28nm_a0_patch_afe_config_init()
134 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d); in bcm7xxx_28nm_a0_patch_afe_config_init()
137 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015); in bcm7xxx_28nm_a0_patch_afe_config_init()
139 bcm_phy_r_rc_cal_reset(phydev); in bcm7xxx_28nm_a0_patch_afe_config_init()
144 static int bcm7xxx_28nm_config_init(struct phy_device *phydev) in bcm7xxx_28nm_config_init() argument
146 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); in bcm7xxx_28nm_config_init()
147 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); in bcm7xxx_28nm_config_init()
155 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_config_init()
158 phydev_name(phydev), phydev->drv->name, rev, patch); in bcm7xxx_28nm_config_init()
165 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_config_init()
170 ret = bcm_phy_28nm_a0b0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
173 ret = bcm7xxx_28nm_d0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
179 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
182 ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
191 ret = bcm_phy_enable_jumbo(phydev); in bcm7xxx_28nm_config_init()
195 ret = bcm_phy_downshift_get(phydev, &count); in bcm7xxx_28nm_config_init()
200 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_config_init()
204 return bcm_phy_enable_apd(phydev, true); in bcm7xxx_28nm_config_init()
207 static int bcm7xxx_28nm_resume(struct phy_device *phydev) in bcm7xxx_28nm_resume() argument
212 ret = bcm7xxx_28nm_config_init(phydev); in bcm7xxx_28nm_resume()
221 return genphy_config_aneg(phydev); in bcm7xxx_28nm_resume()
255 static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_01_afe_config_init() argument
260 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_01_afe_config_init()
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
275 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
285 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
292 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
301 static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_apd_enable() argument
306 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, in bcm7xxx_28nm_ephy_apd_enable()
312 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, in bcm7xxx_28nm_ephy_apd_enable()
318 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0, in bcm7xxx_28nm_ephy_apd_enable()
326 static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_eee_enable() argument
331 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_eee_enable()
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
351 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
356 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
360 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
366 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
370 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
377 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
383 phy_write(phydev, MII_BMCR, in bcm7xxx_28nm_ephy_eee_enable()
389 static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_config_init() argument
391 u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_ephy_config_init()
395 phydev_name(phydev), phydev->drv->name, rev); in bcm7xxx_28nm_ephy_config_init()
402 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_ephy_config_init()
406 ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev); in bcm7xxx_28nm_ephy_config_init()
411 ret = bcm7xxx_28nm_ephy_eee_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
415 return bcm7xxx_28nm_ephy_apd_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
445 static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev, in bcm7xxx_28nm_ephy_read_mmd() argument
456 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_read_mmd()
462 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd); in bcm7xxx_28nm_ephy_read_mmd()
466 ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT); in bcm7xxx_28nm_ephy_read_mmd()
470 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_read_mmd()
475 static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev, in bcm7xxx_28nm_ephy_write_mmd() argument
486 ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_write_mmd()
492 ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd); in bcm7xxx_28nm_ephy_write_mmd()
497 __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val); in bcm7xxx_28nm_ephy_write_mmd()
501 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_write_mmd()
505 static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev) in bcm7xxx_28nm_ephy_resume() argument
510 ret = bcm7xxx_28nm_ephy_config_init(phydev); in bcm7xxx_28nm_ephy_resume()
514 return genphy_config_aneg(phydev); in bcm7xxx_28nm_ephy_resume()
517 static int bcm7xxx_config_init(struct phy_device *phydev) in bcm7xxx_config_init() argument
522 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO); in bcm7xxx_config_init()
523 phy_read(phydev, MII_BCM7XXX_AUX_MODE); in bcm7xxx_config_init()
526 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_config_init()
532 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
536 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
538 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
541 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
551 static int bcm7xxx_suspend(struct phy_device *phydev) in bcm7xxx_suspend() argument
568 ret = phy_write(phydev, in bcm7xxx_suspend()
578 static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev, in bcm7xxx_28nm_get_tunable() argument
584 return bcm_phy_downshift_get(phydev, (u8 *)data); in bcm7xxx_28nm_get_tunable()
590 static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev, in bcm7xxx_28nm_set_tunable() argument
599 ret = bcm_phy_downshift_set(phydev, count); in bcm7xxx_28nm_set_tunable()
612 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_set_tunable()
616 return genphy_restart_aneg(phydev); in bcm7xxx_28nm_set_tunable()
619 static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev, in bcm7xxx_28nm_get_phy_stats() argument
622 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_get_phy_stats()
624 bcm_phy_get_stats(phydev, priv->stats, stats, data); in bcm7xxx_28nm_get_phy_stats()
627 static int bcm7xxx_28nm_probe(struct phy_device *phydev) in bcm7xxx_28nm_probe() argument
632 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in bcm7xxx_28nm_probe()
636 phydev->priv = priv; in bcm7xxx_28nm_probe()
638 priv->stats = devm_kcalloc(&phydev->mdio.dev, in bcm7xxx_28nm_probe()
639 bcm_phy_get_sset_count(phydev), sizeof(u64), in bcm7xxx_28nm_probe()
644 priv->clk = devm_clk_get_optional(&phydev->mdio.dev, NULL); in bcm7xxx_28nm_probe()
658 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_probe()
663 static void bcm7xxx_28nm_remove(struct phy_device *phydev) in bcm7xxx_28nm_remove() argument
665 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_remove()