Lines Matching +full:0 +full:x00000504
68 #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038
70 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c
71 #define ENABLE_FMASK GENMASK(0, 0)
90 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044
91 #define RX_FMASK GENMASK(0, 0)
122 #define IPA_REG_ROUTE_OFFSET 0x00000048
123 #define ROUTE_DIS_FMASK GENMASK(0, 0)
130 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054
131 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0)
134 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074
135 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0)
138 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078
139 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0)
141 /* The next two fields are present for IPA v4.0 and above */
148 return 0x0000010c; in ipa_reg_state_aggr_active_offset()
150 return 0x000000b4; in ipa_reg_state_aggr_active_offset()
155 #define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148
156 #define IPV6_ROUTER_HASH_EN GENMASK(0, 0)
164 return 0x0000090; in ipa_reg_filt_rout_hash_flush_offset()
166 return 0x000014c; in ipa_reg_filt_rout_hash_flush_offset()
169 #define IPV6_ROUTER_HASH_FLUSH GENMASK(0, 0)
174 #define IPA_REG_BCR_OFFSET 0x000001d0
175 #define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0)
192 return 0x00000000; in ipa_reg_bcr_val()
195 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8
197 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec
203 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0
214 #define IPA_REG_TX_CFG_OFFSET 0x000001fc
216 #define TX0_PREFETCH_DISABLE GENMASK(0, 0)
219 /* The next fields are present for IPA v4.0 and above */
230 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210
231 #define BAM_MAX_PIPES_FMASK GENMASK(4, 0)
239 return 0x00000240; in ipa_reg_idle_indication_cfg_offset()
241 return 0x00000220; in ipa_reg_idle_indication_cfg_offset()
244 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0)
248 (0x00000400 + 0x0020 * (rt))
250 (0x00000404 + 0x0020 * (rt))
252 (0x00000408 + 0x0020 * (rt))
254 (0x00000500 + 0x0020 * (rt))
256 (0x00000504 + 0x0020 * (rt))
258 (0x00000508 + 0x0020 * (rt))
259 #define X_MIN_LIM_FMASK GENMASK(5, 0)
265 (0x00000800 + 0x0070 * (ep))
266 #define ENDP_SUSPEND_FMASK GENMASK(0, 0)
270 (0x00000808 + 0x0070 * (ep))
271 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0)
277 (0x00000810 + 0x0070 * (ep))
278 #define HDR_LEN_FMASK GENMASK(5, 0)
289 (0x00000814 + 0x0070 * (ep))
290 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0)
299 (0x00000818 + 0x0070 * (rxep))
303 (0x00000820 + 0x0070 * (txep))
304 #define MODE_FMASK GENMASK(2, 0)
312 (0x00000824 + 0x0070 * (ep))
313 #define AGGR_EN_FMASK GENMASK(1, 0)
324 (0x0000082c + 0x0070 * (rxep))
325 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0)
329 (0x00000830 + 0x0070 * (rxep))
331 #define BASE_VALUE_FMASK GENMASK(4, 0)
336 (0x00000834 + 0x0070 * (txep))
337 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0)
343 (0x00000838 + 0x0070 * (ep))
344 #define RSRC_GRP_FMASK GENMASK(1, 0)
348 (0x0000083c + 0x0070 * (txep))
349 #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0)
355 (0x00000840 + 0x0070 * (ep))
356 #define STATUS_EN_FMASK GENMASK(0, 0)
359 /* The next field is present for IPA v4.0 and above */
364 (0x0000085c + 0x0070 * (er))
365 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0)
372 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0)
386 (0x00003008 + 0x1000 * (ee))
391 (0x0000300c + 0x1000 * (ee))
396 (0x00003010 + 0x1000 * (ee))
401 (0x0000301c + 0x1000 * (ee))
406 (0x00003030 + 0x1000 * (ee))
412 (0x00003034 + 0x1000 * (ee))
418 (0x00003038 + 0x1000 * (ee))
423 IPA_CS_OFFLOAD_NONE = 0,
431 IPA_BYPASS_AGGR = 0,
438 IPA_MBIM_16 = 0,
449 IPA_BASIC = 0,
472 IPA_SEQ_DMA_ONLY = 0x0000,
473 IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002,
474 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004,
475 IPA_SEQ_DMA_DEC = 0x0011,
476 IPA_SEQ_DMA_COMP_DECOMP = 0x0020,
477 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806,
478 IPA_SEQ_INVALID = 0xffff,