73 #define nw64(reg, val)		writeq((val), np->regs + (reg))  macro
201 	nw64(reg, bits);  in __niu_set_and_wait_clear()
222 	nw64(LDG_IMGMT(lp->ldg_num), val);  in niu_ldg_rearm()
246 	nw64(mask_reg, val);  in niu_ldn_irq_enable()
317 	nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));  in mdio_read()
322 	nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));  in mdio_read()
330 	nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));  in mdio_write()
335 	nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));  in mdio_write()
345 	nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));  in mii_read()
353 	nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));  in mii_write()
799 	nw64(ctrl_reg, ctrl_val);  in serdes_init_10g()
800 	nw64(test_cfg_reg, test_cfg_val);  in serdes_init_10g()
902 	nw64(ENET_SERDES_1_PLL_CFG, val);  in serdes_init_1g()
960 	nw64(ENET_SERDES_RESET, reset_val);  in serdes_init_1g_serdes()
964 	nw64(pll_cfg, val);  in serdes_init_1g_serdes()
965 	nw64(ctrl_reg, ctrl_val);  in serdes_init_1g_serdes()
966 	nw64(test_cfg_reg, test_cfg_val);  in serdes_init_1g_serdes()
967 	nw64(ENET_SERDES_RESET, val_rd);  in serdes_init_1g_serdes()
1551 	nw64(MIF_CONFIG, val);  in xcvr_init_10g_bcm8706()
1608 	nw64(MIF_CONFIG, val);  in xcvr_init_10g()
1661 	nw64(MIF_CONFIG, val);  in xcvr_init_1g_rgmii()
1855 	nw64(MIF_CONFIG, val);  in xcvr_init_1g()
2397 	nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);  in serdes_init_10g_serdes()
2398 	nw64(ctrl_reg, ctrl_val);  in serdes_init_10g_serdes()
2399 	nw64(test_cfg_reg, test_cfg_val);  in serdes_init_10g_serdes()
2762 	nw64(ENET_VLAN_TBL(index), reg_val);  in vlan_tbl_write()
2770 		nw64(ENET_VLAN_TBL(i), 0);  in vlan_tbl_clear()
2790 	nw64(TCAM_KEY_0, 0x00);  in tcam_flush()
2791 	nw64(TCAM_KEY_MASK_0, 0xff);  in tcam_flush()
2792 	nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));  in tcam_flush()
2803 	nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2822 	nw64(TCAM_KEY_0, key[0]);  in tcam_write()
2823 	nw64(TCAM_KEY_1, key[1]);  in tcam_write()
2824 	nw64(TCAM_KEY_2, key[2]);  in tcam_write()
2825 	nw64(TCAM_KEY_3, key[3]);  in tcam_write()
2826 	nw64(TCAM_KEY_MASK_0, mask[0]);  in tcam_write()
2827 	nw64(TCAM_KEY_MASK_1, mask[1]);  in tcam_write()
2828 	nw64(TCAM_KEY_MASK_2, mask[2]);  in tcam_write()
2829 	nw64(TCAM_KEY_MASK_3, mask[3]);  in tcam_write()
2830 	nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));  in tcam_write()
2840 	nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2851 	nw64(TCAM_KEY_1, assoc_data);  in tcam_assoc_write()
2852 	nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));  in tcam_assoc_write()
2865 	nw64(FFLP_CFG_1, val);  in tcam_enable()
2877 	nw64(FFLP_CFG_1, val);  in tcam_set_lat_and_ratio()
2881 	nw64(FFLP_CFG_1, val);  in tcam_set_lat_and_ratio()
2900 	nw64(reg, val);  in tcam_user_eth_class_enable()
2921 	nw64(reg, val);
2943 	nw64(reg, val);  in tcam_user_ip_class_enable()
2971 	nw64(reg, val);  in tcam_user_ip_class_set()
3028 	nw64(HASH_TBL_ADDR(partition), val);
3047 	nw64(HASH_TBL_ADDR(partition), val);  in hash_write()
3049 		nw64(HASH_TBL_DATA(partition), data[i]);  in hash_write()
3058 	nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);  in fflp_reset()
3060 	nw64(FFLP_CFG_1, 0);  in fflp_reset()
3063 	nw64(FFLP_CFG_1, val);  in fflp_reset()
3072 	nw64(FFLP_CFG_1, val);  in fflp_set_timings()
3076 	nw64(FFLP_CFG_1, val);  in fflp_set_timings()
3082 	nw64(FCRAM_REF_TMR, val);  in fflp_set_timings()
3104 	nw64(reg, val);  in fflp_set_partition()
3129 	nw64(FFLP_CFG_1, val);  in fflp_llcsnap_enable()
3140 	nw64(FFLP_CFG_1, val);  in fflp_errors_enable()
3191 		nw64(H1POLY, 0);  in fflp_early_init()
3192 		nw64(H2POLY, 0);  in fflp_early_init()
3225 	nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);  in niu_set_flow_key()
3235 	nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);  in niu_set_tcam_key()
3358 			nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);  in niu_rbr_refill()
3651 		nw64(RXMISC(rx_channel), 0);  in niu_sync_rx_discard_stats()
3666 		nw64(RED_DIS_CNT(rx_channel), 0);  in niu_sync_rx_discard_stats()
3718 	nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);  in niu_rx_work()
3741 		nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);  in niu_poll_core()
3756 		nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);  in niu_poll_core()
3832 	nw64(RX_DMA_CTL_STAT(rp->rx_channel),  in niu_rx_error()
4080 						nw64(RX_DMA_CTL_STAT(rp->rx_channel),  in niu_slowpath_interrupt()
4131 	nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);  in niu_rxchan_intr()
4162 		nw64(LD_IM0(ldn), LD_IM0_MASK);  in __niu_fastpath_interrupt()
4174 		nw64(LD_IM0(ldn), LD_IM0_MASK);  in __niu_fastpath_interrupt()
4556 	nw64(TX_CS(channel), val);  in niu_tx_channel_stop()
4579 	nw64(TX_CS(channel), val);  in niu_tx_channel_reset()
4583 		nw64(TX_RING_KICK(channel), 0);  in niu_tx_channel_reset()
4592 	nw64(TX_LOG_MASK1(channel), 0);  in niu_tx_channel_lpage_init()
4593 	nw64(TX_LOG_VAL1(channel), 0);  in niu_tx_channel_lpage_init()
4594 	nw64(TX_LOG_MASK2(channel), 0);  in niu_tx_channel_lpage_init()
4595 	nw64(TX_LOG_VAL2(channel), 0);  in niu_tx_channel_lpage_init()
4596 	nw64(TX_LOG_PAGE_RELO1(channel), 0);  in niu_tx_channel_lpage_init()
4597 	nw64(TX_LOG_PAGE_RELO2(channel), 0);  in niu_tx_channel_lpage_init()
4598 	nw64(TX_LOG_PAGE_HDL(channel), 0);  in niu_tx_channel_lpage_init()
4602 	nw64(TX_LOG_PAGE_VLD(channel), val);  in niu_tx_channel_lpage_init()
4624 	nw64(TXC_CONTROL, val);  in niu_txc_enable_port()
4650 	nw64(TXC_PORT_DMA(np->port), val);  in niu_txc_port_dma_enable()
4670 	nw64(TXC_DMA_MAX(channel), rp->max_burst);  in niu_init_one_tx_channel()
4671 	nw64(TX_ENT_MSK(channel), 0);  in niu_init_one_tx_channel()
4689 	nw64(TX_RNG_CFIG(channel), val);  in niu_init_one_tx_channel()
4697 	nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);  in niu_init_one_tx_channel()
4698 	nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);  in niu_init_one_tx_channel()
4700 	nw64(TX_CS(channel), 0);  in niu_init_one_tx_channel()
4718 			nw64(RDC_TBL(this_table, slot),  in niu_init_rdc_groups()
4722 	nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);  in niu_init_rdc_groups()
4740 	nw64(PT_DRR_WT(np->port), val);  in niu_init_drr_weight()
4778 	nw64(RX_LOG_MASK1(channel), 0);  in niu_rx_channel_lpage_init()
4779 	nw64(RX_LOG_VAL1(channel), 0);  in niu_rx_channel_lpage_init()
4780 	nw64(RX_LOG_MASK2(channel), 0);  in niu_rx_channel_lpage_init()
4781 	nw64(RX_LOG_VAL2(channel), 0);  in niu_rx_channel_lpage_init()
4782 	nw64(RX_LOG_PAGE_RELO1(channel), 0);  in niu_rx_channel_lpage_init()
4783 	nw64(RX_LOG_PAGE_RELO2(channel), 0);  in niu_rx_channel_lpage_init()
4784 	nw64(RX_LOG_PAGE_HDL(channel), 0);  in niu_rx_channel_lpage_init()
4788 	nw64(RX_LOG_PAGE_VLD(channel), val);  in niu_rx_channel_lpage_init()
4801 	nw64(RDC_RED_PARA(rp->rx_channel), val);  in niu_rx_channel_wred_init()
4893 	nw64(RXDMA_CFIG1(channel), val);  in niu_enable_rx_channel()
4921 	nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);  in niu_init_one_rx_channel()
4922 	nw64(RX_DMA_CTL_STAT(channel),  in niu_init_one_rx_channel()
4927 	nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);  in niu_init_one_rx_channel()
4928 	nw64(RXDMA_CFIG2(channel),  in niu_init_one_rx_channel()
4931 	nw64(RBR_CFIG_A(channel),  in niu_init_one_rx_channel()
4937 	nw64(RBR_CFIG_B(channel), val);  in niu_init_one_rx_channel()
4938 	nw64(RCRCFIG_A(channel),  in niu_init_one_rx_channel()
4941 	nw64(RCRCFIG_B(channel),  in niu_init_one_rx_channel()
4950 	nw64(RBR_KICK(channel), rp->rbr_index);  in niu_init_one_rx_channel()
4954 	nw64(RX_DMA_CTL_STAT(channel), val);  in niu_init_one_rx_channel()
4966 	nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);  in niu_init_rx_channels()
4967 	nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));  in niu_init_rx_channels()
5026 	nw64(H1POLY, cp->h1_init);  in niu_init_classifier_hw()
5027 	nw64(H2POLY, cp->h2_init);  in niu_init_classifier_hw()
5071 	nw64(ZCP_RAM_DATA0, data[0]);  in niu_zcp_write()
5072 	nw64(ZCP_RAM_DATA1, data[1]);  in niu_zcp_write()
5073 	nw64(ZCP_RAM_DATA2, data[2]);  in niu_zcp_write()
5074 	nw64(ZCP_RAM_DATA3, data[3]);  in niu_zcp_write()
5075 	nw64(ZCP_RAM_DATA4, data[4]);  in niu_zcp_write()
5076 	nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);  in niu_zcp_write()
5077 	nw64(ZCP_RAM_ACC,  in niu_zcp_write()
5098 	nw64(ZCP_RAM_ACC,  in niu_zcp_read()
5125 	nw64(RESET_CFIFO, val);  in niu_zcp_cfifo_reset()
5129 	nw64(RESET_CFIFO, val);  in niu_zcp_cfifo_reset()
5161 	nw64(CFIFO_ECC(np->port), 0);  in niu_init_zcp()
5162 	nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);  in niu_init_zcp()
5164 	nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);  in niu_init_zcp()
5277 		nw64(MIF_CONFIG, val);  in niu_init_xif_xmac()
5872 	nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);  in niu_reset_one_rx_channel()
5873 	nw64(RX_DMA_CTL_STAT(channel), 0);  in niu_reset_one_rx_channel()
6711 	nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));  in niu_start_xmit()
7310 		nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);  in niu_set_hash_opts()
7322 			nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),  in niu_set_hash_opts()
7334 	nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);  in niu_set_hash_opts()
7918 		nw64(LDG_NUM(ldn), ldg);  in niu_ldg_assign_ldn()
7929 	nw64(LDG_TIMER_RES, res);  in niu_set_ldg_timer_res()
7941 	nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);  in niu_set_ldg_sid()
7956 	nw64(ESPC_PIO_STAT, frame);  in niu_pci_eeprom_read()
7971 	nw64(ESPC_PIO_STAT, frame);  in niu_pci_eeprom_read()
9285 		nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);  in niu_get_invariants()
9294 		nw64(ESPC_PIO_EN, 0);  in niu_get_invariants()