72 #define nr64(reg)		readq(np->regs + (reg))  macro
179 		u64 val = nr64(reg);  in __niu_wait_bits_clear()
206 			   (unsigned long long)nr64(reg));  in __niu_set_and_wait_clear()
241 	val = nr64(mask_reg);  in niu_ldn_irq_enable()
303 		val = nr64(MIF_FRAME_OUTPUT);  in mdio_wait()
508 		sig = nr64(ESR_INT_SIGNALS);  in serdes_init_niu_1g_serdes()
614 		sig = nr64(ESR_INT_SIGNALS);  in serdes_init_niu_10g_serdes()
838 	sig = nr64(ESR_INT_SIGNALS);  in serdes_init_10g()
884 	val = nr64(ENET_SERDES_1_PLL_CFG);  in serdes_init_1g()
962 	val_rd = nr64(ENET_SERDES_RESET);  in serdes_init_1g_serdes()
1003 	sig = nr64(ESR_INT_SIGNALS);  in serdes_init_1g_serdes()
1549 	val = nr64(MIF_CONFIG);  in xcvr_init_10g_bcm8706()
1606 	val = nr64(MIF_CONFIG);  in xcvr_init_10g()
1659 	val = nr64(MIF_CONFIG);  in xcvr_init_1g_rgmii()
1853 	val = nr64(MIF_CONFIG);  in xcvr_init_1g()
2108 	sig = nr64(ESR_INT_SIGNALS);  in niu_10g_phy_present()
2435 	sig = nr64(ESR_INT_SIGNALS);  in serdes_init_10g_serdes()
2750 	u64 reg_val = nr64(ENET_VLAN_TBL(index));  in vlan_tbl_write()
2778 		if (nr64(TCAM_CTL) & bit)  in tcam_wait_bit()
2806 		key[0] = nr64(TCAM_KEY_0);
2807 		key[1] = nr64(TCAM_KEY_1);
2808 		key[2] = nr64(TCAM_KEY_2);
2809 		key[3] = nr64(TCAM_KEY_3);
2810 		mask[0] = nr64(TCAM_KEY_MASK_0);
2811 		mask[1] = nr64(TCAM_KEY_MASK_1);
2812 		mask[2] = nr64(TCAM_KEY_MASK_2);
2813 		mask[3] = nr64(TCAM_KEY_MASK_3);
2843 		*data = nr64(TCAM_KEY_1);
2859 	u64 val = nr64(FFLP_CFG_1);  in tcam_enable()
2870 	u64 val = nr64(FFLP_CFG_1);  in tcam_set_lat_and_ratio()
2879 	val = nr64(FFLP_CFG_1);  in tcam_set_lat_and_ratio()
2895 	val = nr64(reg);  in tcam_user_eth_class_enable()
2918 	val = nr64(reg);
2938 	val = nr64(reg);  in tcam_user_ip_class_enable()
2963 	val = nr64(reg);  in tcam_user_ip_class_set()
3030 		data[i] = nr64(HASH_TBL_DATA(partition));
3068 	u64 val = nr64(FFLP_CFG_1);  in fflp_set_timings()
3074 	val = nr64(FFLP_CFG_1);  in fflp_set_timings()
3078 	val = nr64(FCRAM_REF_TMR);  in fflp_set_timings()
3098 	val = nr64(reg);  in fflp_set_partition()
3123 	u64 val = nr64(FFLP_CFG_1);  in fflp_llcsnap_enable()
3134 	u64 val = nr64(FFLP_CFG_1);  in fflp_errors_enable()
3649 	misc = nr64(RXMISC(rx_channel));  in niu_sync_rx_discard_stats()
3664 	wred = nr64(RED_DIS_CNT(rx_channel));  in niu_sync_rx_discard_stats()
3686 	stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));  in niu_rx_work()
3687 	qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;  in niu_rx_work()
3816 	u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));  in niu_rx_error()
3867 	cs = nr64(TX_CS(rp->tx_channel));  in niu_tx_error()
3868 	logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));  in niu_tx_error()
3869 	logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));  in niu_tx_error()
3884 	u64 mif_status = nr64(MIF_STATUS);  in niu_mif_interrupt()
4048 	u64 stat = nr64(SYS_ERR_STAT);  in niu_device_error()
4140 	rp->tx_cs = nr64(TX_CS(rp->tx_channel));  in niu_txchan_intr()
4206 	v0 = nr64(LDSV0(ldg));  in niu_interrupt()
4207 	v1 = nr64(LDSV1(ldg));  in niu_interrupt()
4208 	v2 = nr64(LDSV2(ldg));  in niu_interrupt()
4544 		u64 val = nr64(TX_CS(channel));  in niu_tx_cs_sng_poll()
4553 	u64 val = nr64(TX_CS(channel));  in niu_tx_channel_stop()
4566 		u64 val = nr64(TX_CS(channel));  in niu_tx_cs_reset_poll()
4575 	u64 val = nr64(TX_CS(channel));  in niu_tx_channel_reset()
4615 	val = nr64(TXC_CONTROL);  in niu_txc_enable_port()
4634 	val = nr64(TXC_INT_MASK);  in niu_txc_set_imask()
4886 	u64 val = nr64(RXDMA_CFIG1(channel));  in niu_enable_rx_channel()
4897 		if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)  in niu_enable_rx_channel()
4952 	val = nr64(RX_DMA_CTL_STAT(channel));  in niu_init_one_rx_channel()
5094 			   (unsigned long long)nr64(ZCP_RAM_ACC));  in niu_zcp_read()
5107 			   (unsigned long long)nr64(ZCP_RAM_ACC));  in niu_zcp_read()
5111 	data[0] = nr64(ZCP_RAM_DATA0);  in niu_zcp_read()
5112 	data[1] = nr64(ZCP_RAM_DATA1);  in niu_zcp_read()
5113 	data[2] = nr64(ZCP_RAM_DATA2);  in niu_zcp_read()
5114 	data[3] = nr64(ZCP_RAM_DATA3);  in niu_zcp_read()
5115 	data[4] = nr64(ZCP_RAM_DATA4);  in niu_zcp_read()
5122 	u64 val = nr64(RESET_CFIFO);  in niu_zcp_cfifo_reset()
5163 	(void) nr64(ZCP_INT_STAT);  in niu_init_zcp()
5275 		val = nr64(MIF_CONFIG);  in niu_init_xif_xmac()
6881 		val = nr64(ESPC_NCR((offset - b_offset) / 4));  in niu_get_eeprom()
6888 		val = nr64(ESPC_NCR(offset / 4));  in niu_get_eeprom()
6895 		val = nr64(ESPC_NCR(offset / 4));  in niu_get_eeprom()
7911 		if (nr64(LDG_NUM(ldn)) != ldg) {  in niu_ldg_assign_ldn()
7914 				(unsigned long long) nr64(LDG_NUM(ldn)));  in niu_ldg_assign_ldn()
7960 		frame = nr64(ESPC_PIO_STAT);  in niu_pci_eeprom_read()
7975 		frame = nr64(ESPC_PIO_STAT);  in niu_pci_eeprom_read()
7985 	frame = nr64(ESPC_PIO_STAT);  in niu_pci_eeprom_read()
8362 	val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);  in niu_pci_probe_sprom()
8373 		val = nr64(ESPC_NCR(i));  in niu_pci_probe_sprom()
8386 	val = nr64(ESPC_PHY_TYPE);  in niu_pci_probe_sprom()
8446 	val = nr64(ESPC_MAC_ADDR0);  in niu_pci_probe_sprom()
8454 	val = nr64(ESPC_MAC_ADDR1);  in niu_pci_probe_sprom()
8471 	val = nr64(ESPC_MOD_STR_LEN);  in niu_pci_probe_sprom()
8478 		u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));  in niu_pci_probe_sprom()
8487 	val = nr64(ESPC_BD_MOD_STR_LEN);  in niu_pci_probe_sprom()
8494 		u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));  in niu_pci_probe_sprom()
8504 		nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;  in niu_pci_probe_sprom()
8527 				parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &  in niu_get_and_validate_port()