78 		void __iomem *ioaddr, bool correctable,  in dwmac5_handle_mac_err()  argument
83 	value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS);  in dwmac5_handle_mac_err()
84 	writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS);  in dwmac5_handle_mac_err()
126 		void __iomem *ioaddr, bool correctable,  in dwmac5_handle_mtl_err()  argument
131 	value = readl(ioaddr + MTL_ECC_INT_STATUS);  in dwmac5_handle_mtl_err()
132 	writel(value, ioaddr + MTL_ECC_INT_STATUS);  in dwmac5_handle_mtl_err()
174 		void __iomem *ioaddr, bool correctable,  in dwmac5_handle_dma_err()  argument
179 	value = readl(ioaddr + DMA_ECC_INT_STATUS);  in dwmac5_handle_dma_err()
180 	writel(value, ioaddr + DMA_ECC_INT_STATUS);  in dwmac5_handle_dma_err()
186 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp)  in dwmac5_safety_feat_config()  argument
194 	value = readl(ioaddr + MTL_ECC_CONTROL);  in dwmac5_safety_feat_config()
200 	writel(value, ioaddr + MTL_ECC_CONTROL);  in dwmac5_safety_feat_config()
203 	value = readl(ioaddr + MTL_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
208 	writel(value, ioaddr + MTL_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
211 	value = readl(ioaddr + DMA_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
213 	writel(value, ioaddr + DMA_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
220 	value = readl(ioaddr + MAC_FSM_CONTROL);  in dwmac5_safety_feat_config()
223 	writel(value, ioaddr + MAC_FSM_CONTROL);  in dwmac5_safety_feat_config()
226 	value = readl(ioaddr + MTL_DPP_CONTROL);  in dwmac5_safety_feat_config()
228 	writel(value, ioaddr + MTL_DPP_CONTROL);  in dwmac5_safety_feat_config()
238 	writel(value, ioaddr + MTL_DPP_CONTROL);  in dwmac5_safety_feat_config()
243 		void __iomem *ioaddr, unsigned int asp,  in dwmac5_safety_feat_irq_status()  argument
253 	mtl = readl(ioaddr + MTL_SAFETY_INT_STATUS);  in dwmac5_safety_feat_irq_status()
254 	dma = readl(ioaddr + DMA_SAFETY_INT_STATUS);  in dwmac5_safety_feat_irq_status()
259 		dwmac5_handle_mac_err(ndev, ioaddr, corr, stats);  in dwmac5_safety_feat_irq_status()
266 		dwmac5_handle_mtl_err(ndev, ioaddr, corr, stats);  in dwmac5_safety_feat_irq_status()
273 		dwmac5_handle_dma_err(ndev, ioaddr, corr, stats);  in dwmac5_safety_feat_irq_status()
305 static int dwmac5_rxp_disable(void __iomem *ioaddr)  in dwmac5_rxp_disable()  argument
310 	val = readl(ioaddr + MTL_OPERATION_MODE);  in dwmac5_rxp_disable()
312 	writel(val, ioaddr + MTL_OPERATION_MODE);  in dwmac5_rxp_disable()
314 	ret = readl_poll_timeout(ioaddr + MTL_RXP_CONTROL_STATUS, val,  in dwmac5_rxp_disable()
321 static void dwmac5_rxp_enable(void __iomem *ioaddr)  in dwmac5_rxp_enable()  argument
325 	val = readl(ioaddr + MTL_OPERATION_MODE);  in dwmac5_rxp_enable()
327 	writel(val, ioaddr + MTL_OPERATION_MODE);  in dwmac5_rxp_enable()
330 static int dwmac5_rxp_update_single_entry(void __iomem *ioaddr,  in dwmac5_rxp_update_single_entry()  argument
341 		ret = readl_poll_timeout(ioaddr + MTL_RXP_IACC_CTRL_STATUS,  in dwmac5_rxp_update_single_entry()
348 		writel(val, ioaddr + MTL_RXP_IACC_DATA);  in dwmac5_rxp_update_single_entry()
352 		writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);  in dwmac5_rxp_update_single_entry()
356 		writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);  in dwmac5_rxp_update_single_entry()
360 		writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);  in dwmac5_rxp_update_single_entry()
363 		ret = readl_poll_timeout(ioaddr + MTL_RXP_IACC_CTRL_STATUS,  in dwmac5_rxp_update_single_entry()
412 int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,  in dwmac5_rxp_config()  argument
421 	old_val = readl(ioaddr + GMAC_CONFIG);  in dwmac5_rxp_config()
423 	writel(val, ioaddr + GMAC_CONFIG);  in dwmac5_rxp_config()
426 	ret = dwmac5_rxp_disable(ioaddr);  in dwmac5_rxp_config()
453 		ret = dwmac5_rxp_update_single_entry(ioaddr, entry, nve);  in dwmac5_rxp_config()
461 			ret = dwmac5_rxp_update_single_entry(ioaddr, frag, nve);  in dwmac5_rxp_config()
478 		ret = dwmac5_rxp_update_single_entry(ioaddr, entry, nve);  in dwmac5_rxp_config()
488 	writel(val, ioaddr + MTL_RXP_CONTROL_STATUS);  in dwmac5_rxp_config()
491 	dwmac5_rxp_enable(ioaddr);  in dwmac5_rxp_config()
495 	writel(old_val, ioaddr + GMAC_CONFIG);  in dwmac5_rxp_config()
499 int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,  in dwmac5_flex_pps_config()  argument
503 	u32 tnsec = readl(ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index));  in dwmac5_flex_pps_config()
504 	u32 val = readl(ioaddr + MAC_PPS_CONTROL);  in dwmac5_flex_pps_config()
519 		writel(val, ioaddr + MAC_PPS_CONTROL);  in dwmac5_flex_pps_config()
527 	writel(cfg->start.tv_sec, ioaddr + MAC_PPSx_TARGET_TIME_SEC(index));  in dwmac5_flex_pps_config()
531 	writel(cfg->start.tv_nsec, ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index));  in dwmac5_flex_pps_config()
541 	writel(period - 1, ioaddr + MAC_PPSx_INTERVAL(index));  in dwmac5_flex_pps_config()
547 	writel(period - 1, ioaddr + MAC_PPSx_WIDTH(index));  in dwmac5_flex_pps_config()
550 	writel(val, ioaddr + MAC_PPS_CONTROL);  in dwmac5_flex_pps_config()
554 static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)  in dwmac5_est_write()  argument
558 	writel(val, ioaddr + MTL_EST_GCL_DATA);  in dwmac5_est_write()
563 	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);  in dwmac5_est_write()
566 	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);  in dwmac5_est_write()
568 	return readl_poll_timeout(ioaddr + MTL_EST_GCL_CONTROL,  in dwmac5_est_write()
572 int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,  in dwmac5_est_configure()  argument
578 	ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);  in dwmac5_est_configure()
579 	ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);  in dwmac5_est_configure()
580 	ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false);  in dwmac5_est_configure()
581 	ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);  in dwmac5_est_configure()
582 	ret |= dwmac5_est_write(ioaddr, CTR_LOW, cfg->ctr[0], false);  in dwmac5_est_configure()
583 	ret |= dwmac5_est_write(ioaddr, CTR_HIGH, cfg->ctr[1], false);  in dwmac5_est_configure()
588 		ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i], true);  in dwmac5_est_configure()
593 	ctrl = readl(ioaddr + MTL_EST_CONTROL);  in dwmac5_est_configure()
601 	writel(ctrl, ioaddr + MTL_EST_CONTROL);  in dwmac5_est_configure()
605 void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,  in dwmac5_fpe_configure()  argument
611 		value = readl(ioaddr + MAC_FPE_CTRL_STS);  in dwmac5_fpe_configure()
615 		writel(value, ioaddr + MAC_FPE_CTRL_STS);  in dwmac5_fpe_configure()
619 	value = readl(ioaddr + GMAC_RXQ_CTRL1);  in dwmac5_fpe_configure()
622 	writel(value, ioaddr + GMAC_RXQ_CTRL1);  in dwmac5_fpe_configure()
624 	value = readl(ioaddr + MAC_FPE_CTRL_STS);  in dwmac5_fpe_configure()
626 	writel(value, ioaddr + MAC_FPE_CTRL_STS);  in dwmac5_fpe_configure()