stmicro/stmmac/dwmac4.h

54 #define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
56 #define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
58 #define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
60 #define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
62 #define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
68 #define GMAC_RXQCTRL_FPRQ		GENMASK(26, 24)
89 #define GMAC_VLAN_VID			GENMASK(15, 0)
92 #define GMAC_VLAN_VLC			GENMASK(17, 16)
94 #define GMAC_VLAN_VLHT			GENMASK(15, 0)
97 #define GMAC_VLAN_TAG_VID		GENMASK(15, 0)
103 #define GMAC_VLAN_TAG_CTRL_OFS_MASK	GENMASK(6, 2)
105 #define GMAC_VLAN_TAG_CTRL_EVLS_MASK	GENMASK(22, 21)
115 #define GMAC_VLAN_TAG_DATA_VID		GENMASK(15, 0)
120 #define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
128 #define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
132 #define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
191 #define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
198 #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
204 #define GMAC_CONFIG_SARC		GENMASK(30, 28)
207 #define GMAC_CONFIG_IPG			GENMASK(26, 24)
224 #define GMAC_CONFIG_EIPG		GENMASK(29, 25)
227 #define GMAC_CONFIG_HDSMS		GENMASK(22, 20)
250 #define GMAC_HW_FEAT_L3L4FNUM		GENMASK(30, 27)
251 #define GMAC_HW_HASH_TB_SZ		GENMASK(25, 24)
255 #define GMAC_HW_ADDR64			GENMASK(15, 14)
256 #define GMAC_HW_TXFIFOSIZE		GENMASK(10, 6)
257 #define GMAC_HW_RXFIFOSIZE		GENMASK(4, 0)
260 #define GMAC_HW_FEAT_PPSOUTNUM		GENMASK(26, 24)
261 #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
262 #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
263 #define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
264 #define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
267 #define GMAC_HW_FEAT_ASP		GENMASK(29, 28)
270 #define GMAC_HW_FEAT_ESTWID		GENMASK(21, 20)
271 #define GMAC_HW_FEAT_ESTDEP		GENMASK(19, 17)
273 #define GMAC_HW_FEAT_FRPES		GENMASK(14, 13)
274 #define GMAC_HW_FEAT_FRPBS		GENMASK(12, 11)
277 #define GMAC_HW_FEAT_NRVF		GENMASK(2, 0)
280 #define GMAC_HI_DCS			GENMASK(18, 16)
295 #define GMAC_L4DP0			GENMASK(31, 16)
297 #define GMAC_L4SP0			GENMASK(15, 0)
302 #define MTL_OPERATION_SCHALG_MASK	GENMASK(6, 5)
316 #define MTL_RXQ_DMA_Q04MDMACH_MASK	GENMASK(3, 0)
318 #define MTL_RXQ_DMA_QXMDMACH_MASK(x)	GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
333 #define MTL_OP_MODE_TXQEN_MASK		GENMASK(3, 2)
338 #define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
353 #define MTL_OP_MODE_RQS_MASK		GENMASK(29, 20)
356 #define MTL_OP_MODE_RFD_MASK		GENMASK(19, 14)
359 #define MTL_OP_MODE_RFA_MASK		GENMASK(13, 8)
386 #define MTL_TXQ_WEIGHT_ISCQW_MASK	GENMASK(20, 0)
394 #define MTL_SEND_SLP_CRED_SSC_MASK	GENMASK(13, 0)
402 #define MTL_HIGH_CRED_HC_MASK		GENMASK(28, 0)
410 #define MTL_HIGH_CRED_LC_MASK		GENMASK(28, 0)
418 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
427 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
433 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
459 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
468 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
474 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
487 #define GMAC_PHYIF_CTRLSTATUS_SPEED		GENMASK(18, 17)