3  * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
74 	int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
96 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,  in meson8b_dwmac_mask_bits()  argument
101 	data = readl(dwmac->regs + reg);  in meson8b_dwmac_mask_bits()
105 	writel(data, dwmac->regs + reg);  in meson8b_dwmac_mask_bits()
108 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,  in meson8b_dwmac_register_clk()  argument
118 	snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),  in meson8b_dwmac_register_clk()
129 	return devm_clk_register(dwmac->dev, hw);  in meson8b_dwmac_register_clk()
132 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)  in meson8b_init_rgmii_tx_clk()  argument
135 	struct device *dev = dwmac->dev;  in meson8b_init_rgmii_tx_clk()
156 	clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;  in meson8b_init_rgmii_tx_clk()
160 	clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,  in meson8b_init_rgmii_tx_clk()
167 	clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;  in meson8b_init_rgmii_tx_clk()
173 	clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_data, 1,  in meson8b_init_rgmii_tx_clk()
182 	clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_data, 1,  in meson8b_init_rgmii_tx_clk()
189 	clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;  in meson8b_init_rgmii_tx_clk()
191 	clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_data, 1,  in meson8b_init_rgmii_tx_clk()
197 	dwmac->rgmii_tx_clk = clk;  in meson8b_init_rgmii_tx_clk()
202 static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)  in meson8b_set_phy_mode()  argument
204 	switch (dwmac->phy_mode) {  in meson8b_set_phy_mode()
210 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,  in meson8b_set_phy_mode()
216 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,  in meson8b_set_phy_mode()
220 		dev_err(dwmac->dev, "fail to set phy-mode %s\n",  in meson8b_set_phy_mode()
221 			phy_modes(dwmac->phy_mode));  in meson8b_set_phy_mode()
228 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)  in meson_axg_set_phy_mode()  argument
230 	switch (dwmac->phy_mode) {  in meson_axg_set_phy_mode()
236 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,  in meson_axg_set_phy_mode()
242 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,  in meson_axg_set_phy_mode()
247 		dev_err(dwmac->dev, "fail to set phy-mode %s\n",  in meson_axg_set_phy_mode()
248 			phy_modes(dwmac->phy_mode));  in meson_axg_set_phy_mode()
255 static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac,  in meson8b_devm_clk_prepare_enable()  argument
264 	return devm_add_action_or_reset(dwmac->dev,  in meson8b_devm_clk_prepare_enable()
269 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)  in meson8b_init_prg_eth()  argument
275 				   dwmac->tx_delay_ns >> 1);  in meson8b_init_prg_eth()
277 	if (dwmac->rx_delay_ns == 2)  in meson8b_init_prg_eth()
282 	switch (dwmac->phy_mode) {  in meson8b_init_prg_eth()
297 		dev_err(dwmac->dev, "unsupported phy-mode %s\n",  in meson8b_init_prg_eth()
298 			phy_modes(dwmac->phy_mode));  in meson8b_init_prg_eth()
303 		if (!dwmac->timing_adj_clk) {  in meson8b_init_prg_eth()
304 			dev_err(dwmac->dev,  in meson8b_init_prg_eth()
310 		ret = meson8b_devm_clk_prepare_enable(dwmac,  in meson8b_init_prg_eth()
311 						      dwmac->timing_adj_clk);  in meson8b_init_prg_eth()
313 			dev_err(dwmac->dev,  in meson8b_init_prg_eth()
319 	meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK |  in meson8b_init_prg_eth()
324 	if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) {  in meson8b_init_prg_eth()
326 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,  in meson8b_init_prg_eth()
334 		ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);  in meson8b_init_prg_eth()
336 			dev_err(dwmac->dev,  in meson8b_init_prg_eth()
341 		ret = meson8b_devm_clk_prepare_enable(dwmac,  in meson8b_init_prg_eth()
342 						      dwmac->rgmii_tx_clk);  in meson8b_init_prg_eth()
344 			dev_err(dwmac->dev,  in meson8b_init_prg_eth()
350 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,  in meson8b_init_prg_eth()
356 	meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,  in meson8b_init_prg_eth()
366 	struct meson8b_dwmac *dwmac;  in meson8b_dwmac_probe()  local
377 	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);  in meson8b_dwmac_probe()
378 	if (!dwmac) {  in meson8b_dwmac_probe()
383 	dwmac->data = (const struct meson8b_dwmac_data *)  in meson8b_dwmac_probe()
385 	if (!dwmac->data) {  in meson8b_dwmac_probe()
389 	dwmac->regs = devm_platform_ioremap_resource(pdev, 1);  in meson8b_dwmac_probe()
390 	if (IS_ERR(dwmac->regs)) {  in meson8b_dwmac_probe()
391 		ret = PTR_ERR(dwmac->regs);  in meson8b_dwmac_probe()
395 	dwmac->dev = &pdev->dev;  in meson8b_dwmac_probe()
396 	ret = of_get_phy_mode(pdev->dev.of_node, &dwmac->phy_mode);  in meson8b_dwmac_probe()
404 				 &dwmac->tx_delay_ns))  in meson8b_dwmac_probe()
405 		dwmac->tx_delay_ns = 2;  in meson8b_dwmac_probe()
409 				 &dwmac->rx_delay_ns))  in meson8b_dwmac_probe()
410 		dwmac->rx_delay_ns = 0;  in meson8b_dwmac_probe()
412 	if (dwmac->rx_delay_ns != 0 && dwmac->rx_delay_ns != 2) {  in meson8b_dwmac_probe()
419 	dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,  in meson8b_dwmac_probe()
421 	if (IS_ERR(dwmac->timing_adj_clk)) {  in meson8b_dwmac_probe()
422 		ret = PTR_ERR(dwmac->timing_adj_clk);  in meson8b_dwmac_probe()
426 	ret = meson8b_init_rgmii_tx_clk(dwmac);  in meson8b_dwmac_probe()
430 	ret = dwmac->data->set_phy_mode(dwmac);  in meson8b_dwmac_probe()
434 	ret = meson8b_init_prg_eth(dwmac);  in meson8b_dwmac_probe()
438 	plat_dat->bsp_priv = dwmac;  in meson8b_dwmac_probe()
462 		.compatible = "amlogic,meson8b-dwmac",
466 		.compatible = "amlogic,meson8m2-dwmac",
470 		.compatible = "amlogic,meson-gxbb-dwmac",
474 		.compatible = "amlogic,meson-axg-dwmac",
478 		.compatible = "amlogic,meson-g12a-dwmac",
489 		.name           = "meson8b-dwmac",
497 MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer");