209 #define sw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
339 	sw32(cr, rfcrSave | RELOAD);  in sis635_get_mac_addr()
340 	sw32(cr, 0);  in sis635_get_mac_addr()
343 	sw32(rfcr, rfcrSave & ~RFEN);  in sis635_get_mac_addr()
347 		sw32(rfcr, (i << RFADDR_shift));  in sis635_get_mac_addr()
352 	sw32(rfcr, rfcrSave | RFEN);  in sis635_get_mac_addr()
380 	sw32(mear, EEREQ);  in sis96x_get_mac_addr()
395 	sw32(mear, EEDONE);  in sis96x_get_mac_addr()
543 		sw32(cr, ACCESSMODE | sr32(cr));  in sis900_probe()
822 	sw32(mear, 0);  in read_eeprom()
824 	sw32(mear, EECS);  in read_eeprom()
831 		sw32(mear, dataval);  in read_eeprom()
833 		sw32(mear, dataval | EECLK);  in read_eeprom()
836 	sw32(mear, EECS);  in read_eeprom()
841 		sw32(mear, EECS);  in read_eeprom()
843 		sw32(mear, EECS | EECLK);  in read_eeprom()
850 	sw32(mear, 0);  in read_eeprom()
865 	sw32(mear, MDIO | MDDIR);  in mdio_idle()
867 	sw32(mear, MDIO | MDDIR | MDC);  in mdio_idle()
877 		sw32(mear, MDDIR | MDIO);  in mdio_reset()
879 		sw32(mear, MDDIR | MDIO | MDC);  in mdio_reset()
909 		sw32(mear, dataval);  in mdio_read()
911 		sw32(mear, dataval | MDC);  in mdio_read()
917 		sw32(mear, 0);  in mdio_read()
920 		sw32(mear, MDC);  in mdio_read()
923 	sw32(mear, 0x00);  in mdio_read()
966 		sw32(mear, dataval);  in mdio_write()
968 		sw32(mear, dataval | MDC);  in mdio_write()
980 	sw32(mear, 0x00);  in mdio_write()
1063 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);  in sis900_open()
1064 	sw32(cr, RxENA | sr32(cr));  in sis900_open()
1065 	sw32(ier, IE);  in sis900_open()
1097 	sw32(rfcr, rfcrSave & ~RFEN);  in sis900_init_rxfilter()
1103 		sw32(rfcr, i << RFADDR_shift);  in sis900_init_rxfilter()
1104 		sw32(rfdr, w);  in sis900_init_rxfilter()
1113 	sw32(rfcr, rfcrSave | RFEN);  in sis900_init_rxfilter()
1143 	sw32(txdp, sis_priv->tx_ring_dma);  in sis900_init_tx_ring()
1204 	sw32(rxdp, sis_priv->rx_ring_dma);  in sis900_init_rx_ring()
1378 		sw32(cfg, ~EXD & sr32(cfg));  in sis900_check_mode()
1382 		sw32(cfg, EXD | sr32(cfg));  in sis900_check_mode()
1436 	sw32(txcfg, tx_flags);  in sis900_set_mode()
1437 	sw32(rxcfg, rx_flags);  in sis900_set_mode()
1555 	sw32(imr, 0x0000);  in sis900_tx_timeout()
1584 	sw32(txdp, sis_priv->tx_ring_dma);  in sis900_tx_timeout()
1587 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);  in sis900_tx_timeout()
1629 	sw32(cr, TxENA | sr32(cr));  in sis900_start_xmit()
1879 	sw32(cr , RxENA | sr32(cr));  in sis900_rx()
1973 	sw32(imr, 0x0000);  in sis900_close()
1974 	sw32(ier, 0x0000);  in sis900_close()
1977 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_close()
2095 		sw32(pmctrl, pmctrl_bits);  in sis900_set_wol()
2110 	sw32(pmctrl, pmctrl_bits);  in sis900_set_wol()
2153 		sw32(mear, EEREQ);  in sis900_read_eeprom()
2164 		sw32(mear, EEDONE);  in sis900_read_eeprom()
2419 		sw32(rfcr, (u32)(0x00000004 + i) << RFADDR_shift);  in set_rx_mode()
2420 		sw32(rfdr, mc_filter[i]);  in set_rx_mode()
2423 	sw32(rfcr, RFEN | rx_mode);  in set_rx_mode()
2431 		sw32(cr, cr_saved | TxDIS | RxDIS);  in set_rx_mode()
2433 		sw32(txcfg, sr32(txcfg) | TxMLB);  in set_rx_mode()
2434 		sw32(rxcfg, sr32(rxcfg) | RxATX);  in set_rx_mode()
2436 		sw32(cr, cr_saved);  in set_rx_mode()
2456 	sw32(ier, 0);  in sis900_reset()
2457 	sw32(imr, 0);  in sis900_reset()
2458 	sw32(rfcr, 0);  in sis900_reset()
2460 	sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));  in sis900_reset()
2468 		sw32(cfg, PESEL | RND_CNT);  in sis900_reset()
2470 		sw32(cfg, PESEL);  in sis900_reset()
2515 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_suspend()
2543 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);  in sis900_resume()
2544 	sw32(cr, RxENA | sr32(cr));  in sis900_resume()
2545 	sw32(ier, IE);  in sis900_resume()