211 #define sr32(reg)	ioread32(ioaddr + (reg))  macro
337 	rfcrSave = sr32(rfcr);  in sis635_get_mac_addr()
382 		if (sr32(mear) & EEGNT) {  in sis96x_get_mac_addr()
543 		sw32(cr, ACCESSMODE | sr32(cr));  in sis900_probe()
570 	ret = (sr32(CFGPMC) & PMESP) >> 27;  in sis900_probe()
805 #define eeprom_delay()	sr32(mear)
845 		retval = (retval << 1) | ((sr32(mear) & EEDO) ? 1 : 0);  in read_eeprom()
859 #define mdio_delay()	sr32(mear)
919 		retval = (retval << 1) | ((sr32(mear) & MDIO) ? 1 : 0);  in mdio_read()
1064 	sw32(cr, RxENA | sr32(cr));  in sis900_open()
1094 	rfcrSave = sr32(rfcr);  in sis900_init_rxfilter()
1108 			       net_dev->name, i, sr32(rfdr));  in sis900_init_rxfilter()
1146 		       net_dev->name, sr32(txdp));  in sis900_init_tx_ring()
1207 		       net_dev->name, sr32(rxdp));  in sis900_init_rx_ring()
1378 		sw32(cfg, ~EXD & sr32(cfg));  in sis900_check_mode()
1382 		sw32(cfg, EXD | sr32(cfg));  in sis900_check_mode()
1408 	if (sr32( cfg) & EDB_MASTER_EN) {  in sis900_set_mode()
1551 			net_dev->name, sr32(cr), sr32(isr));  in sis900_tx_timeout()
1629 	sw32(cr, TxENA | sr32(cr));  in sis900_start_xmit()
1682 		status = sr32(isr);  in sis900_interrupt()
1717 		       net_dev->name, sr32(isr));  in sis900_interrupt()
1879 	sw32(cr , RxENA | sr32(cr));  in sis900_rx()
1977 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_close()
2127 	pmctrl_bits = sr32(pmctrl);  in sis900_get_wol()
2155 			if (sr32(mear) & EEGNT) {  in sis900_read_eeprom()
2430 		cr_saved = sr32(cr);  in set_rx_mode()
2433 		sw32(txcfg, sr32(txcfg) | TxMLB);  in set_rx_mode()
2434 		sw32(rxcfg, sr32(rxcfg) | RxATX);  in set_rx_mode()
2460 	sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));  in sis900_reset()
2464 		status ^= sr32(isr) & status;  in sis900_reset()
2515 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_suspend()
2544 	sw32(cr, RxENA | sr32(cr));  in sis900_resume()