80 #define RTL_W8(tp, reg, val8)	writeb((val8), tp->mmio_addr + (reg))  argument
81 #define RTL_W16(tp, reg, val16)	writew((val16), tp->mmio_addr + (reg))  argument
82 #define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))  argument
83 #define RTL_R8(tp, reg)		readb(tp->mmio_addr + (reg))  argument
84 #define RTL_R16(tp, reg)		readw(tp->mmio_addr + (reg))  argument
85 #define RTL_R32(tp, reg)		readl(tp->mmio_addr + (reg))  argument
636 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
665 static inline struct device *tp_to_dev(struct rtl8169_private *tp)  in tp_to_dev()  argument
667 	return &tp->pci_dev->dev;  in tp_to_dev()
670 static void rtl_lock_config_regs(struct rtl8169_private *tp)  in rtl_lock_config_regs()  argument
672 	RTL_W8(tp, Cfg9346, Cfg9346_Lock);  in rtl_lock_config_regs()
675 static void rtl_unlock_config_regs(struct rtl8169_private *tp)  in rtl_unlock_config_regs()  argument
677 	RTL_W8(tp, Cfg9346, Cfg9346_Unlock);  in rtl_unlock_config_regs()
680 static void rtl_pci_commit(struct rtl8169_private *tp)  in rtl_pci_commit()  argument
683 	RTL_R8(tp, ChipCmd);  in rtl_pci_commit()
686 static bool rtl_is_8125(struct rtl8169_private *tp)  in rtl_is_8125()  argument
688 	return tp->mac_version >= RTL_GIGA_MAC_VER_60;  in rtl_is_8125()
691 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)  in rtl_is_8168evl_up()  argument
693 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_is_8168evl_up()
694 	       tp->mac_version != RTL_GIGA_MAC_VER_39 &&  in rtl_is_8168evl_up()
695 	       tp->mac_version <= RTL_GIGA_MAC_VER_52;  in rtl_is_8168evl_up()
698 static bool rtl_supports_eee(struct rtl8169_private *tp)  in rtl_supports_eee()  argument
700 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_supports_eee()
701 	       tp->mac_version != RTL_GIGA_MAC_VER_37 &&  in rtl_supports_eee()
702 	       tp->mac_version != RTL_GIGA_MAC_VER_39;  in rtl_supports_eee()
726 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)  in rtl_read_mac_from_reg()  argument
731 		mac[i] = RTL_R8(tp, reg + i);  in rtl_read_mac_from_reg()
739 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,  in rtl_loop_wait()  argument
745 		if (c->check(tp) == high)  in rtl_loop_wait()
751 		netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",  in rtl_loop_wait()
756 static bool rtl_loop_wait_high(struct rtl8169_private *tp,  in rtl_loop_wait_high()  argument
760 	return rtl_loop_wait(tp, c, d, n, true);  in rtl_loop_wait_high()
763 static bool rtl_loop_wait_low(struct rtl8169_private *tp,  in rtl_loop_wait_low()  argument
767 	return rtl_loop_wait(tp, c, d, n, false);  in rtl_loop_wait_low()
778 static bool name ## _check(struct rtl8169_private *tp)
780 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)  in rtl_ocp_reg_failure()  argument
784 			netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);  in rtl_ocp_reg_failure()
792 	return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;  in DECLARE_RTL_COND()
795 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_phy_ocp_write()  argument
797 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_phy_ocp_write()
800 	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);  in r8168_phy_ocp_write()
802 	rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);  in r8168_phy_ocp_write()
805 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_phy_ocp_read()  argument
807 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_phy_ocp_read()
810 	RTL_W32(tp, GPHY_OCP, reg << 15);  in r8168_phy_ocp_read()
812 	return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?  in r8168_phy_ocp_read()
813 		(RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;  in r8168_phy_ocp_read()
816 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_mac_ocp_write()  argument
818 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_mac_ocp_write()
821 	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);  in r8168_mac_ocp_write()
824 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_mac_ocp_read()  argument
826 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_mac_ocp_read()
829 	RTL_W32(tp, OCPDR, reg << 15);  in r8168_mac_ocp_read()
831 	return RTL_R32(tp, OCPDR);  in r8168_mac_ocp_read()
834 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,  in r8168_mac_ocp_modify()  argument
837 	u16 data = r8168_mac_ocp_read(tp, reg);  in r8168_mac_ocp_modify()
839 	r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);  in r8168_mac_ocp_modify()
842 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168g_mdio_write()  argument
845 		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;  in r8168g_mdio_write()
849 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_write()
852 	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);  in r8168g_mdio_write()
855 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)  in r8168g_mdio_read()  argument
858 		return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;  in r8168g_mdio_read()
860 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_read()
863 	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);  in r8168g_mdio_read()
866 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)  in mac_mcu_write()  argument
869 		tp->ocp_base = value << 4;  in mac_mcu_write()
873 	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);  in mac_mcu_write()
876 static int mac_mcu_read(struct rtl8169_private *tp, int reg)  in mac_mcu_read()  argument
878 	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);  in mac_mcu_read()
883 	return RTL_R32(tp, PHYAR) & 0x80000000;  in DECLARE_RTL_COND()
886 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8169_mdio_write()  argument
888 	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));  in r8169_mdio_write()
890 	rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);  in r8169_mdio_write()
898 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)  in r8169_mdio_read()  argument
902 	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);  in r8169_mdio_read()
904 	value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?  in r8169_mdio_read()
905 		RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;  in r8169_mdio_read()
918 	return RTL_R32(tp, OCPAR) & OCPAR_FLAG;  in DECLARE_RTL_COND()
921 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)  in r8168dp_1_mdio_access()  argument
923 	RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));  in r8168dp_1_mdio_access()
924 	RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);  in r8168dp_1_mdio_access()
925 	RTL_W32(tp, EPHY_RXER_NUM, 0);  in r8168dp_1_mdio_access()
927 	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);  in r8168dp_1_mdio_access()
930 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168dp_1_mdio_write()  argument
932 	r8168dp_1_mdio_access(tp, reg,  in r8168dp_1_mdio_write()
936 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)  in r8168dp_1_mdio_read()  argument
938 	r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);  in r8168dp_1_mdio_read()
941 	RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);  in r8168dp_1_mdio_read()
942 	RTL_W32(tp, EPHY_RXER_NUM, 0);  in r8168dp_1_mdio_read()
944 	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?  in r8168dp_1_mdio_read()
945 		RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;  in r8168dp_1_mdio_read()
950 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)  in r8168dp_2_mdio_start()  argument
952 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_start()
955 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)  in r8168dp_2_mdio_stop()  argument
957 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_stop()
960 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168dp_2_mdio_write()  argument
962 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_write()
964 	r8169_mdio_write(tp, reg, value);  in r8168dp_2_mdio_write()
966 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_write()
969 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)  in r8168dp_2_mdio_read()  argument
977 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_read()
979 	value = r8169_mdio_read(tp, reg);  in r8168dp_2_mdio_read()
981 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_read()
986 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)  in rtl_writephy()  argument
988 	switch (tp->mac_version) {  in rtl_writephy()
990 		r8168dp_1_mdio_write(tp, location, val);  in rtl_writephy()
994 		r8168dp_2_mdio_write(tp, location, val);  in rtl_writephy()
997 		r8168g_mdio_write(tp, location, val);  in rtl_writephy()
1000 		r8169_mdio_write(tp, location, val);  in rtl_writephy()
1005 static int rtl_readphy(struct rtl8169_private *tp, int location)  in rtl_readphy()  argument
1007 	switch (tp->mac_version) {  in rtl_readphy()
1009 		return r8168dp_1_mdio_read(tp, location);  in rtl_readphy()
1012 		return r8168dp_2_mdio_read(tp, location);  in rtl_readphy()
1014 		return r8168g_mdio_read(tp, location);  in rtl_readphy()
1016 		return r8169_mdio_read(tp, location);  in rtl_readphy()
1022 	return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;  in DECLARE_RTL_COND()
1025 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)  in rtl_ephy_write()  argument
1027 	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |  in rtl_ephy_write()
1030 	rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);  in rtl_ephy_write()
1035 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)  in rtl_ephy_read()  argument
1037 	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);  in rtl_ephy_read()
1039 	return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?  in rtl_ephy_read()
1040 		RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;  in rtl_ephy_read()
1043 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)  in r8168fp_adjust_ocp_cmd()  argument
1046 	if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)  in r8168fp_adjust_ocp_cmd()
1052 	return RTL_R32(tp, ERIAR) & ERIAR_FLAG;  in DECLARE_RTL_COND()
1055 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in _rtl_eri_write()  argument
1061 	RTL_W32(tp, ERIDR, val);  in _rtl_eri_write()
1062 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_write()
1063 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_write()
1065 	rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);  in _rtl_eri_write()
1068 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in rtl_eri_write()  argument
1071 	_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);  in rtl_eri_write()
1074 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)  in _rtl_eri_read()  argument
1078 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_read()
1079 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_read()
1081 	return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?  in _rtl_eri_read()
1082 		RTL_R32(tp, ERIDR) : ~0;  in _rtl_eri_read()
1085 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)  in rtl_eri_read()  argument
1087 	return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);  in rtl_eri_read()
1090 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)  in rtl_w0w1_eri()  argument
1092 	u32 val = rtl_eri_read(tp, addr);  in rtl_w0w1_eri()
1094 	rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);  in rtl_w0w1_eri()
1097 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)  in rtl_eri_set_bits()  argument
1099 	rtl_w0w1_eri(tp, addr, p, 0);  in rtl_eri_set_bits()
1102 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)  in rtl_eri_clear_bits()  argument
1104 	rtl_w0w1_eri(tp, addr, 0, m);  in rtl_eri_clear_bits()
1107 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168dp_ocp_read()  argument
1109 	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));  in r8168dp_ocp_read()
1110 	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?  in r8168dp_ocp_read()
1111 		RTL_R32(tp, OCPDR) : ~0;  in r8168dp_ocp_read()
1114 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168ep_ocp_read()  argument
1116 	return _rtl_eri_read(tp, reg, ERIAR_OOB);  in r8168ep_ocp_read()
1119 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168dp_ocp_write()  argument
1122 	RTL_W32(tp, OCPDR, data);  in r8168dp_ocp_write()
1123 	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));  in r8168dp_ocp_write()
1124 	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);  in r8168dp_ocp_write()
1127 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168ep_ocp_write()  argument
1130 	_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,  in r8168ep_ocp_write()
1134 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)  in r8168dp_oob_notify()  argument
1136 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);  in r8168dp_oob_notify()
1138 	r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);  in r8168dp_oob_notify()
1145 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)  in rtl8168_get_ocp_reg()  argument
1147 	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;  in rtl8168_get_ocp_reg()
1154 	reg = rtl8168_get_ocp_reg(tp);  in DECLARE_RTL_COND()
1156 	return r8168dp_ocp_read(tp, reg) & 0x00000800;  in DECLARE_RTL_COND()
1161 	return r8168ep_ocp_read(tp, 0x124) & 0x00000001;  in DECLARE_RTL_COND()
1166 	return RTL_R8(tp, IBISR0) & 0x20;  in DECLARE_RTL_COND()
1169 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)  in rtl8168ep_stop_cmac()  argument
1171 	RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);  in rtl8168ep_stop_cmac()
1172 	rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);  in rtl8168ep_stop_cmac()
1173 	RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);  in rtl8168ep_stop_cmac()
1174 	RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);  in rtl8168ep_stop_cmac()
1177 static void rtl8168dp_driver_start(struct rtl8169_private *tp)  in rtl8168dp_driver_start()  argument
1179 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);  in rtl8168dp_driver_start()
1180 	rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_start()
1183 static void rtl8168ep_driver_start(struct rtl8169_private *tp)  in rtl8168ep_driver_start()  argument
1185 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);  in rtl8168ep_driver_start()
1186 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_start()
1187 	rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);  in rtl8168ep_driver_start()
1190 static void rtl8168_driver_start(struct rtl8169_private *tp)  in rtl8168_driver_start()  argument
1192 	switch (tp->mac_version) {  in rtl8168_driver_start()
1196 		rtl8168dp_driver_start(tp);  in rtl8168_driver_start()
1199 		rtl8168ep_driver_start(tp);  in rtl8168_driver_start()
1207 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)  in rtl8168dp_driver_stop()  argument
1209 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);  in rtl8168dp_driver_stop()
1210 	rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_stop()
1213 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)  in rtl8168ep_driver_stop()  argument
1215 	rtl8168ep_stop_cmac(tp);  in rtl8168ep_driver_stop()
1216 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);  in rtl8168ep_driver_stop()
1217 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_stop()
1218 	rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);  in rtl8168ep_driver_stop()
1221 static void rtl8168_driver_stop(struct rtl8169_private *tp)  in rtl8168_driver_stop()  argument
1223 	switch (tp->mac_version) {  in rtl8168_driver_stop()
1227 		rtl8168dp_driver_stop(tp);  in rtl8168_driver_stop()
1230 		rtl8168ep_driver_stop(tp);  in rtl8168_driver_stop()
1238 static bool r8168dp_check_dash(struct rtl8169_private *tp)  in r8168dp_check_dash()  argument
1240 	u16 reg = rtl8168_get_ocp_reg(tp);  in r8168dp_check_dash()
1242 	return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);  in r8168dp_check_dash()
1245 static bool r8168ep_check_dash(struct rtl8169_private *tp)  in r8168ep_check_dash()  argument
1247 	return r8168ep_ocp_read(tp, 0x128) & 0x00000001;  in r8168ep_check_dash()
1250 static bool r8168_check_dash(struct rtl8169_private *tp)  in r8168_check_dash()  argument
1252 	switch (tp->mac_version) {  in r8168_check_dash()
1256 		return r8168dp_check_dash(tp);  in r8168_check_dash()
1258 		return r8168ep_check_dash(tp);  in r8168_check_dash()
1264 static void rtl_reset_packet_filter(struct rtl8169_private *tp)  in rtl_reset_packet_filter()  argument
1266 	rtl_eri_clear_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1267 	rtl_eri_set_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1272 	return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;  in DECLARE_RTL_COND()
1275 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)  in rtl8168d_efuse_read()  argument
1277 	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);  in rtl8168d_efuse_read()
1279 	return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?  in rtl8168d_efuse_read()
1280 		RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;  in rtl8168d_efuse_read()
1283 static u32 rtl_get_events(struct rtl8169_private *tp)  in rtl_get_events()  argument
1285 	if (rtl_is_8125(tp))  in rtl_get_events()
1286 		return RTL_R32(tp, IntrStatus_8125);  in rtl_get_events()
1288 		return RTL_R16(tp, IntrStatus);  in rtl_get_events()
1291 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)  in rtl_ack_events()  argument
1293 	if (rtl_is_8125(tp))  in rtl_ack_events()
1294 		RTL_W32(tp, IntrStatus_8125, bits);  in rtl_ack_events()
1296 		RTL_W16(tp, IntrStatus, bits);  in rtl_ack_events()
1299 static void rtl_irq_disable(struct rtl8169_private *tp)  in rtl_irq_disable()  argument
1301 	if (rtl_is_8125(tp))  in rtl_irq_disable()
1302 		RTL_W32(tp, IntrMask_8125, 0);  in rtl_irq_disable()
1304 		RTL_W16(tp, IntrMask, 0);  in rtl_irq_disable()
1307 static void rtl_irq_enable(struct rtl8169_private *tp)  in rtl_irq_enable()  argument
1309 	if (rtl_is_8125(tp))  in rtl_irq_enable()
1310 		RTL_W32(tp, IntrMask_8125, tp->irq_mask);  in rtl_irq_enable()
1312 		RTL_W16(tp, IntrMask, tp->irq_mask);  in rtl_irq_enable()
1315 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)  in rtl8169_irq_mask_and_ack()  argument
1317 	rtl_irq_disable(tp);  in rtl8169_irq_mask_and_ack()
1318 	rtl_ack_events(tp, 0xffffffff);  in rtl8169_irq_mask_and_ack()
1319 	rtl_pci_commit(tp);  in rtl8169_irq_mask_and_ack()
1322 static void rtl_link_chg_patch(struct rtl8169_private *tp)  in rtl_link_chg_patch()  argument
1324 	struct phy_device *phydev = tp->phydev;  in rtl_link_chg_patch()
1326 	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||  in rtl_link_chg_patch()
1327 	    tp->mac_version == RTL_GIGA_MAC_VER_38) {  in rtl_link_chg_patch()
1329 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1330 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1332 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1333 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1335 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1336 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1338 		rtl_reset_packet_filter(tp);  in rtl_link_chg_patch()
1339 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||  in rtl_link_chg_patch()
1340 		   tp->mac_version == RTL_GIGA_MAC_VER_36) {  in rtl_link_chg_patch()
1342 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1343 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1345 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1346 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1348 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {  in rtl_link_chg_patch()
1350 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);  in rtl_link_chg_patch()
1351 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);  in rtl_link_chg_patch()
1353 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_link_chg_patch()
1362 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_wol()  local
1365 	wol->wolopts = tp->saved_wolopts;  in rtl8169_get_wol()
1368 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)  in __rtl8169_set_wol()  argument
1385 	rtl_unlock_config_regs(tp);  in __rtl8169_set_wol()
1387 	if (rtl_is_8168evl_up(tp)) {  in __rtl8169_set_wol()
1390 			rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1392 			rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1393 	} else if (rtl_is_8125(tp)) {  in __rtl8169_set_wol()
1396 			r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));  in __rtl8169_set_wol()
1398 			r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);  in __rtl8169_set_wol()
1402 		options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;  in __rtl8169_set_wol()
1405 		RTL_W8(tp, cfg[i].reg, options);  in __rtl8169_set_wol()
1408 	switch (tp->mac_version) {  in __rtl8169_set_wol()
1410 		options = RTL_R8(tp, Config1) & ~PMEnable;  in __rtl8169_set_wol()
1413 		RTL_W8(tp, Config1, options);  in __rtl8169_set_wol()
1418 		options = RTL_R8(tp, Config2) & ~PME_SIGNAL;  in __rtl8169_set_wol()
1421 		RTL_W8(tp, Config2, options);  in __rtl8169_set_wol()
1427 	rtl_lock_config_regs(tp);  in __rtl8169_set_wol()
1429 	device_set_wakeup_enable(tp_to_dev(tp), wolopts);  in __rtl8169_set_wol()
1430 	tp->dev->wol_enabled = wolopts ? 1 : 0;  in __rtl8169_set_wol()
1435 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_wol()  local
1440 	tp->saved_wolopts = wol->wolopts;  in rtl8169_set_wol()
1441 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_set_wol()
1449 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_drvinfo()  local
1450 	struct rtl_fw *rtl_fw = tp->rtl_fw;  in rtl8169_get_drvinfo()
1453 	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));  in rtl8169_get_drvinfo()
1468 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_fix_features()  local
1474 	    tp->mac_version > RTL_GIGA_MAC_VER_06)  in rtl8169_fix_features()
1480 static void rtl_set_rx_config_features(struct rtl8169_private *tp,  in rtl_set_rx_config_features()  argument
1483 	u32 rx_config = RTL_R32(tp, RxConfig);  in rtl_set_rx_config_features()
1490 	if (rtl_is_8125(tp)) {  in rtl_set_rx_config_features()
1497 	RTL_W32(tp, RxConfig, rx_config);  in rtl_set_rx_config_features()
1503 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_features()  local
1505 	rtl_set_rx_config_features(tp, features);  in rtl8169_set_features()
1508 		tp->cp_cmd |= RxChkSum;  in rtl8169_set_features()
1510 		tp->cp_cmd &= ~RxChkSum;  in rtl8169_set_features()
1512 	if (!rtl_is_8125(tp)) {  in rtl8169_set_features()
1514 			tp->cp_cmd |= RxVlan;  in rtl8169_set_features()
1516 			tp->cp_cmd &= ~RxVlan;  in rtl8169_set_features()
1519 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl8169_set_features()
1520 	rtl_pci_commit(tp);  in rtl8169_set_features()
1542 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_regs()  local
1543 	u32 __iomem *data = tp->mmio_addr;  in rtl8169_get_regs()
1579 	return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);  in DECLARE_RTL_COND()
1582 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)  in rtl8169_do_counters()  argument
1584 	dma_addr_t paddr = tp->counters_phys_addr;  in rtl8169_do_counters()
1587 	RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);  in rtl8169_do_counters()
1588 	rtl_pci_commit(tp);  in rtl8169_do_counters()
1590 	RTL_W32(tp, CounterAddrLow, cmd);  in rtl8169_do_counters()
1591 	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);  in rtl8169_do_counters()
1593 	rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);  in rtl8169_do_counters()
1596 static void rtl8169_reset_counters(struct rtl8169_private *tp)  in rtl8169_reset_counters()  argument
1602 	if (tp->mac_version >= RTL_GIGA_MAC_VER_19)  in rtl8169_reset_counters()
1603 		rtl8169_do_counters(tp, CounterReset);  in rtl8169_reset_counters()
1606 static void rtl8169_update_counters(struct rtl8169_private *tp)  in rtl8169_update_counters()  argument
1608 	u8 val = RTL_R8(tp, ChipCmd);  in rtl8169_update_counters()
1615 		rtl8169_do_counters(tp, CounterDump);  in rtl8169_update_counters()
1618 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)  in rtl8169_init_counter_offsets()  argument
1620 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_init_counter_offsets()
1637 	if (tp->tc_offset.inited)  in rtl8169_init_counter_offsets()
1640 	rtl8169_reset_counters(tp);  in rtl8169_init_counter_offsets()
1641 	rtl8169_update_counters(tp);  in rtl8169_init_counter_offsets()
1643 	tp->tc_offset.tx_errors = counters->tx_errors;  in rtl8169_init_counter_offsets()
1644 	tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;  in rtl8169_init_counter_offsets()
1645 	tp->tc_offset.tx_aborted = counters->tx_aborted;  in rtl8169_init_counter_offsets()
1646 	tp->tc_offset.rx_missed = counters->rx_missed;  in rtl8169_init_counter_offsets()
1647 	tp->tc_offset.inited = true;  in rtl8169_init_counter_offsets()
1653 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_ethtool_stats()  local
1656 	counters = tp->counters;  in rtl8169_get_ethtool_stats()
1657 	rtl8169_update_counters(tp);  in rtl8169_get_ethtool_stats()
1737 rtl_coalesce_info(struct rtl8169_private *tp)  in rtl_coalesce_info()  argument
1741 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_coalesce_info()
1747 	if (tp->phydev->speed == SPEED_UNKNOWN)  in rtl_coalesce_info()
1751 		if (tp->phydev->speed == ci->speed)  in rtl_coalesce_info()
1760 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_get_coalesce()  local
1765 	if (rtl_is_8125(tp))  in rtl_get_coalesce()
1771 	ci = rtl_coalesce_info(tp);  in rtl_get_coalesce()
1775 	scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];  in rtl_get_coalesce()
1777 	intrmit = RTL_R16(tp, IntrMitigate);  in rtl_get_coalesce()
1796 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,  in rtl_coalesce_choose_scale()  argument
1802 	ci = rtl_coalesce_info(tp);  in rtl_coalesce_choose_scale()
1818 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_coalesce()  local
1825 	if (rtl_is_8125(tp))  in rtl_set_coalesce()
1832 	scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);  in rtl_set_coalesce()
1864 	RTL_W16(tp, IntrMitigate, w);  in rtl_set_coalesce()
1867 	if (rtl_is_8168evl_up(tp)) {  in rtl_set_coalesce()
1870 			tp->cp_cmd |= PktCntrDisable;  in rtl_set_coalesce()
1872 			tp->cp_cmd &= ~PktCntrDisable;  in rtl_set_coalesce()
1875 	tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;  in rtl_set_coalesce()
1876 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_set_coalesce()
1877 	rtl_pci_commit(tp);  in rtl_set_coalesce()
1884 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_eee()  local
1886 	if (!rtl_supports_eee(tp))  in rtl8169_get_eee()
1889 	return phy_ethtool_get_eee(tp->phydev, data);  in rtl8169_get_eee()
1894 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_eee()  local
1897 	if (!rtl_supports_eee(tp))  in rtl8169_set_eee()
1900 	ret = phy_ethtool_set_eee(tp->phydev, data);  in rtl8169_set_eee()
1903 		tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,  in rtl8169_set_eee()
1930 static void rtl_enable_eee(struct rtl8169_private *tp)  in rtl_enable_eee()  argument
1932 	struct phy_device *phydev = tp->phydev;  in rtl_enable_eee()
1936 	if (tp->eee_adv >= 0)  in rtl_enable_eee()
1937 		adv = tp->eee_adv;  in rtl_enable_eee()
2070 static void rtl_release_firmware(struct rtl8169_private *tp)  in rtl_release_firmware()  argument
2072 	if (tp->rtl_fw) {  in rtl_release_firmware()
2073 		rtl_fw_release_firmware(tp->rtl_fw);  in rtl_release_firmware()
2074 		kfree(tp->rtl_fw);  in rtl_release_firmware()
2075 		tp->rtl_fw = NULL;  in rtl_release_firmware()
2079 void r8169_apply_firmware(struct rtl8169_private *tp)  in r8169_apply_firmware()  argument
2084 	if (tp->rtl_fw) {  in r8169_apply_firmware()
2085 		rtl_fw_write_firmware(tp, tp->rtl_fw);  in r8169_apply_firmware()
2087 		tp->ocp_base = OCP_STD_PHY_BASE;  in r8169_apply_firmware()
2090 		phy_read_poll_timeout(tp->phydev, MII_BMCR, val,  in r8169_apply_firmware()
2096 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)  in rtl8168_config_eee_mac()  argument
2099 	if (tp->mac_version != RTL_GIGA_MAC_VER_38)  in rtl8168_config_eee_mac()
2100 		RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);  in rtl8168_config_eee_mac()
2102 	rtl_eri_set_bits(tp, 0x1b0, 0x0003);  in rtl8168_config_eee_mac()
2105 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)  in rtl8125a_config_eee_mac()  argument
2107 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125a_config_eee_mac()
2108 	r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));  in rtl8125a_config_eee_mac()
2111 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)  in rtl8125_set_eee_txidle_timer()  argument
2113 	RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);  in rtl8125_set_eee_txidle_timer()
2116 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)  in rtl8125b_config_eee_mac()  argument
2118 	rtl8125_set_eee_txidle_timer(tp);  in rtl8125b_config_eee_mac()
2119 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125b_config_eee_mac()
2122 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)  in rtl_rar_exgmac_set()  argument
2130 	rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));  in rtl_rar_exgmac_set()
2131 	rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);  in rtl_rar_exgmac_set()
2132 	rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);  in rtl_rar_exgmac_set()
2133 	rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));  in rtl_rar_exgmac_set()
2136 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)  in rtl8168h_2_get_adc_bias_ioffset()  argument
2140 	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);  in rtl8168h_2_get_adc_bias_ioffset()
2141 	data1 = r8168_mac_ocp_read(tp, 0xdd02);  in rtl8168h_2_get_adc_bias_ioffset()
2142 	data2 = r8168_mac_ocp_read(tp, 0xdd00);  in rtl8168h_2_get_adc_bias_ioffset()
2152 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)  in rtl_schedule_task()  argument
2154 	set_bit(flag, tp->wk.flags);  in rtl_schedule_task()
2155 	schedule_work(&tp->wk.work);  in rtl_schedule_task()
2158 static void rtl8169_init_phy(struct rtl8169_private *tp)  in rtl8169_init_phy()  argument
2160 	r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);  in rtl8169_init_phy()
2162 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {  in rtl8169_init_phy()
2163 		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);  in rtl8169_init_phy()
2164 		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);  in rtl8169_init_phy()
2166 		RTL_W8(tp, 0x82, 0x01);  in rtl8169_init_phy()
2169 	if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&  in rtl8169_init_phy()
2170 	    tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&  in rtl8169_init_phy()
2171 	    tp->pci_dev->subsystem_device == 0xe000)  in rtl8169_init_phy()
2172 		phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);  in rtl8169_init_phy()
2175 	phy_speed_up(tp->phydev);  in rtl8169_init_phy()
2177 	if (rtl_supports_eee(tp))  in rtl8169_init_phy()
2178 		rtl_enable_eee(tp);  in rtl8169_init_phy()
2180 	genphy_soft_reset(tp->phydev);  in rtl8169_init_phy()
2183 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)  in rtl_rar_set()  argument
2185 	rtl_unlock_config_regs(tp);  in rtl_rar_set()
2187 	RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);  in rtl_rar_set()
2188 	rtl_pci_commit(tp);  in rtl_rar_set()
2190 	RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);  in rtl_rar_set()
2191 	rtl_pci_commit(tp);  in rtl_rar_set()
2193 	if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl_rar_set()
2194 		rtl_rar_exgmac_set(tp, addr);  in rtl_rar_set()
2196 	rtl_lock_config_regs(tp);  in rtl_rar_set()
2201 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_mac_address()  local
2208 	rtl_rar_set(tp, dev->dev_addr);  in rtl_set_mac_address()
2213 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)  in rtl_wol_suspend_quirk()  argument
2215 	switch (tp->mac_version) {  in rtl_wol_suspend_quirk()
2224 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |  in rtl_wol_suspend_quirk()
2232 static void rtl_pll_power_down(struct rtl8169_private *tp)  in rtl_pll_power_down()  argument
2234 	if (r8168_check_dash(tp))  in rtl_pll_power_down()
2237 	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||  in rtl_pll_power_down()
2238 	    tp->mac_version == RTL_GIGA_MAC_VER_33)  in rtl_pll_power_down()
2239 		rtl_ephy_write(tp, 0x19, 0xff64);  in rtl_pll_power_down()
2241 	if (device_may_wakeup(tp_to_dev(tp))) {  in rtl_pll_power_down()
2242 		phy_speed_down(tp->phydev, false);  in rtl_pll_power_down()
2243 		rtl_wol_suspend_quirk(tp);  in rtl_pll_power_down()
2247 	switch (tp->mac_version) {  in rtl_pll_power_down()
2260 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);  in rtl_pll_power_down()
2265 		rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);  in rtl_pll_power_down()
2266 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);  in rtl_pll_power_down()
2273 static void rtl_pll_power_up(struct rtl8169_private *tp)  in rtl_pll_power_up()  argument
2275 	switch (tp->mac_version) {  in rtl_pll_power_up()
2282 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);  in rtl_pll_power_up()
2290 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);  in rtl_pll_power_up()
2295 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);  in rtl_pll_power_up()
2296 		rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);  in rtl_pll_power_up()
2302 	phy_resume(tp->phydev);  in rtl_pll_power_up()
2305 static void rtl_init_rxcfg(struct rtl8169_private *tp)  in rtl_init_rxcfg()  argument
2307 	switch (tp->mac_version) {  in rtl_init_rxcfg()
2310 		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);  in rtl_init_rxcfg()
2315 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2318 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);  in rtl_init_rxcfg()
2321 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);  in rtl_init_rxcfg()
2324 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2329 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)  in rtl8169_init_ring_indexes()  argument
2331 	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;  in rtl8169_init_ring_indexes()
2334 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_enable()  argument
2336 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168c_hw_jumbo_enable()
2337 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);  in r8168c_hw_jumbo_enable()
2340 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_disable()  argument
2342 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168c_hw_jumbo_disable()
2343 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);  in r8168c_hw_jumbo_disable()
2346 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_enable()  argument
2348 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168dp_hw_jumbo_enable()
2351 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_disable()  argument
2353 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168dp_hw_jumbo_disable()
2356 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_enable()  argument
2358 	RTL_W8(tp, MaxTxPacketSize, 0x24);  in r8168e_hw_jumbo_enable()
2359 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168e_hw_jumbo_enable()
2360 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);  in r8168e_hw_jumbo_enable()
2363 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_disable()  argument
2365 	RTL_W8(tp, MaxTxPacketSize, 0x3f);  in r8168e_hw_jumbo_disable()
2366 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168e_hw_jumbo_disable()
2367 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);  in r8168e_hw_jumbo_disable()
2370 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_enable()  argument
2372 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));  in r8168b_1_hw_jumbo_enable()
2375 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_disable()  argument
2377 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));  in r8168b_1_hw_jumbo_disable()
2380 static void rtl_jumbo_config(struct rtl8169_private *tp)  in rtl_jumbo_config()  argument
2382 	bool jumbo = tp->dev->mtu > ETH_DATA_LEN;  in rtl_jumbo_config()
2385 	rtl_unlock_config_regs(tp);  in rtl_jumbo_config()
2386 	switch (tp->mac_version) {  in rtl_jumbo_config()
2391 			r8168b_1_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2393 			r8168b_1_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2399 			r8168c_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2401 			r8168c_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2406 			r8168dp_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2408 			r8168dp_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2412 			pcie_set_readrq(tp->pci_dev, 512);  in rtl_jumbo_config()
2413 			r8168e_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2415 			r8168e_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2421 	rtl_lock_config_regs(tp);  in rtl_jumbo_config()
2423 	if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)  in rtl_jumbo_config()
2424 		pcie_set_readrq(tp->pci_dev, readrq);  in rtl_jumbo_config()
2428 			 tp->phydev->advertising, !jumbo);  in rtl_jumbo_config()
2430 			 tp->phydev->advertising, !jumbo);  in rtl_jumbo_config()
2431 	phy_start_aneg(tp->phydev);  in rtl_jumbo_config()
2436 	return RTL_R8(tp, ChipCmd) & CmdReset;  in DECLARE_RTL_COND()
2439 static void rtl_hw_reset(struct rtl8169_private *tp)  in rtl_hw_reset()  argument
2441 	RTL_W8(tp, ChipCmd, CmdReset);  in rtl_hw_reset()
2443 	rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);  in rtl_hw_reset()
2446 static void rtl_request_firmware(struct rtl8169_private *tp)  in rtl_request_firmware()  argument
2451 	if (tp->rtl_fw || !tp->fw_name)  in rtl_request_firmware()
2462 	rtl_fw->fw_name = tp->fw_name;  in rtl_request_firmware()
2463 	rtl_fw->dev = tp_to_dev(tp);  in rtl_request_firmware()
2468 		tp->rtl_fw = rtl_fw;  in rtl_request_firmware()
2471 static void rtl_rx_close(struct rtl8169_private *tp)  in rtl_rx_close()  argument
2473 	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);  in rtl_rx_close()
2478 	return RTL_R8(tp, TxPoll) & NPQ;  in DECLARE_RTL_COND()
2483 	return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;  in DECLARE_RTL_COND()
2488 	return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;  in DECLARE_RTL_COND()
2494 	return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;  in DECLARE_RTL_COND()
2497 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)  in rtl_wait_txrx_fifo_empty()  argument
2499 	switch (tp->mac_version) {  in rtl_wait_txrx_fifo_empty()
2501 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2502 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2505 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2508 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl_wait_txrx_fifo_empty()
2509 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2510 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);  in rtl_wait_txrx_fifo_empty()
2517 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)  in rtl_enable_rxdvgate()  argument
2519 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);  in rtl_enable_rxdvgate()
2521 	rtl_wait_txrx_fifo_empty(tp);  in rtl_enable_rxdvgate()
2524 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)  in rtl_set_tx_config_registers()  argument
2529 	if (rtl_is_8168evl_up(tp))  in rtl_set_tx_config_registers()
2532 	RTL_W32(tp, TxConfig, val);  in rtl_set_tx_config_registers()
2535 static void rtl_set_rx_max_size(struct rtl8169_private *tp)  in rtl_set_rx_max_size()  argument
2538 	RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);  in rtl_set_rx_max_size()
2541 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)  in rtl_set_rx_tx_desc_registers()  argument
2548 	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2549 	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2550 	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2551 	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2554 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)  in rtl8169_set_magic_reg()  argument
2558 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl8169_set_magic_reg()
2560 	else if (tp->mac_version == RTL_GIGA_MAC_VER_06)  in rtl8169_set_magic_reg()
2565 	if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)  in rtl8169_set_magic_reg()
2568 	RTL_W32(tp, 0x7c, val);  in rtl8169_set_magic_reg()
2576 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_rx_mode()  local
2583 		   tp->mac_version == RTL_GIGA_MAC_VER_35) {  in rtl_set_rx_mode()
2596 		if (tp->mac_version > RTL_GIGA_MAC_VER_06) {  in rtl_set_rx_mode()
2603 	RTL_W32(tp, MAR0 + 4, mc_filter[1]);  in rtl_set_rx_mode()
2604 	RTL_W32(tp, MAR0 + 0, mc_filter[0]);  in rtl_set_rx_mode()
2606 	tmp = RTL_R32(tp, RxConfig);  in rtl_set_rx_mode()
2607 	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);  in rtl_set_rx_mode()
2612 	return RTL_R32(tp, CSIAR) & CSIAR_FLAG;  in DECLARE_RTL_COND()
2615 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)  in rtl_csi_write()  argument
2617 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_write()
2619 	RTL_W32(tp, CSIDR, value);  in rtl_csi_write()
2620 	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in rtl_csi_write()
2623 	rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);  in rtl_csi_write()
2626 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)  in rtl_csi_read()  argument
2628 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_read()
2630 	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |  in rtl_csi_read()
2633 	return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?  in rtl_csi_read()
2634 		RTL_R32(tp, CSIDR) : ~0;  in rtl_csi_read()
2637 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)  in rtl_csi_access_enable()  argument
2639 	struct pci_dev *pdev = tp->pci_dev;  in rtl_csi_access_enable()
2650 	netdev_notice_once(tp->dev,  in rtl_csi_access_enable()
2652 	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;  in rtl_csi_access_enable()
2653 	rtl_csi_write(tp, 0x070c, csi | val << 24);  in rtl_csi_access_enable()
2656 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)  in rtl_set_def_aspm_entry_latency()  argument
2658 	rtl_csi_access_enable(tp, 0x27);  in rtl_set_def_aspm_entry_latency()
2667 static void __rtl_ephy_init(struct rtl8169_private *tp,  in __rtl_ephy_init()  argument
2673 		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;  in __rtl_ephy_init()
2674 		rtl_ephy_write(tp, e->offset, w);  in __rtl_ephy_init()
2679 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))  argument
2681 static void rtl_disable_clock_request(struct rtl8169_private *tp)  in rtl_disable_clock_request()  argument
2683 	pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_disable_clock_request()
2687 static void rtl_enable_clock_request(struct rtl8169_private *tp)  in rtl_enable_clock_request()  argument
2689 	pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_enable_clock_request()
2693 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)  in rtl_pcie_state_l2l3_disable()  argument
2696 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);  in rtl_pcie_state_l2l3_disable()
2699 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)  in rtl_hw_aspm_clkreq_enable()  argument
2702 	if (enable && tp->aspm_manageable) {  in rtl_hw_aspm_clkreq_enable()
2703 		RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);  in rtl_hw_aspm_clkreq_enable()
2704 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);  in rtl_hw_aspm_clkreq_enable()
2706 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);  in rtl_hw_aspm_clkreq_enable()
2707 		RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);  in rtl_hw_aspm_clkreq_enable()
2713 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,  in rtl_set_fifo_size()  argument
2719 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);  in rtl_set_fifo_size()
2720 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);  in rtl_set_fifo_size()
2723 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,  in rtl8168g_set_pause_thresholds()  argument
2727 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);  in rtl8168g_set_pause_thresholds()
2728 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);  in rtl8168g_set_pause_thresholds()
2731 static void rtl_hw_start_8168b(struct rtl8169_private *tp)  in rtl_hw_start_8168b()  argument
2733 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168b()
2736 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)  in __rtl_hw_start_8168cp()  argument
2738 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);  in __rtl_hw_start_8168cp()
2740 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in __rtl_hw_start_8168cp()
2742 	rtl_disable_clock_request(tp);  in __rtl_hw_start_8168cp()
2745 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_1()  argument
2755 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_1()
2757 	rtl_ephy_init(tp, e_info_8168cp);  in rtl_hw_start_8168cp_1()
2759 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168cp_1()
2762 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_2()  argument
2764 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_2()
2766 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_2()
2769 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_3()  argument
2771 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_3()
2773 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_3()
2776 	RTL_W8(tp, DBG_REG, 0x20);  in rtl_hw_start_8168cp_3()
2779 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)  in rtl_hw_start_8168c_1()  argument
2787 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_1()
2789 	RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);  in rtl_hw_start_8168c_1()
2791 	rtl_ephy_init(tp, e_info_8168c_1);  in rtl_hw_start_8168c_1()
2793 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_1()
2796 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)  in rtl_hw_start_8168c_2()  argument
2803 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_2()
2805 	rtl_ephy_init(tp, e_info_8168c_2);  in rtl_hw_start_8168c_2()
2807 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_2()
2810 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)  in rtl_hw_start_8168c_3()  argument
2812 	rtl_hw_start_8168c_2(tp);  in rtl_hw_start_8168c_3()
2815 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)  in rtl_hw_start_8168c_4()  argument
2817 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_4()
2819 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_4()
2822 static void rtl_hw_start_8168d(struct rtl8169_private *tp)  in rtl_hw_start_8168d()  argument
2824 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d()
2826 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168d()
2829 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)  in rtl_hw_start_8168d_4()  argument
2838 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d_4()
2840 	rtl_ephy_init(tp, e_info_8168d_4);  in rtl_hw_start_8168d_4()
2842 	rtl_enable_clock_request(tp);  in rtl_hw_start_8168d_4()
2845 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)  in rtl_hw_start_8168e_1()  argument
2863 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_1()
2865 	rtl_ephy_init(tp, e_info_8168e_1);  in rtl_hw_start_8168e_1()
2867 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_1()
2870 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);  in rtl_hw_start_8168e_1()
2871 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);  in rtl_hw_start_8168e_1()
2873 	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);  in rtl_hw_start_8168e_1()
2876 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)  in rtl_hw_start_8168e_2()  argument
2885 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_2()
2887 	rtl_ephy_init(tp, e_info_8168e_2);  in rtl_hw_start_8168e_2()
2889 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168e_2()
2890 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168e_2()
2891 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168e_2()
2892 	rtl_eri_set_bits(tp, 0x0d4, 0x1f00);  in rtl_hw_start_8168e_2()
2893 	rtl_eri_set_bits(tp, 0x1d0, BIT(1));  in rtl_hw_start_8168e_2()
2894 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168e_2()
2895 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168e_2()
2896 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168e_2()
2897 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);  in rtl_hw_start_8168e_2()
2899 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_2()
2901 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168e_2()
2903 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168e_2()
2905 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168e_2()
2906 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168e_2()
2907 	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);  in rtl_hw_start_8168e_2()
2909 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168e_2()
2912 static void rtl_hw_start_8168f(struct rtl8169_private *tp)  in rtl_hw_start_8168f()  argument
2914 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168f()
2916 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168f()
2917 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168f()
2918 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168f()
2919 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168f()
2920 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168f()
2921 	rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));  in rtl_hw_start_8168f()
2922 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168f()
2923 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);  in rtl_hw_start_8168f()
2925 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168f()
2927 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168f()
2928 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168f()
2929 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168f()
2930 	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);  in rtl_hw_start_8168f()
2932 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168f()
2935 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)  in rtl_hw_start_8168f_1()  argument
2946 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8168f_1()
2948 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8168f_1()
2950 	rtl_eri_set_bits(tp, 0x0d4, 0x1f00);  in rtl_hw_start_8168f_1()
2953 static void rtl_hw_start_8411(struct rtl8169_private *tp)  in rtl_hw_start_8411()  argument
2963 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8411()
2964 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8411()
2966 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8411()
2968 	rtl_eri_set_bits(tp, 0x0d4, 0x0c00);  in rtl_hw_start_8411()
2971 static void rtl_hw_start_8168g(struct rtl8169_private *tp)  in rtl_hw_start_8168g()  argument
2973 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168g()
2974 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168g()
2976 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168g()
2978 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168g()
2979 	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);  in rtl_hw_start_8168g()
2981 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168g()
2983 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
2984 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
2985 	rtl_eri_set_bits(tp, 0x0d4, 0x1f80);  in rtl_hw_start_8168g()
2987 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168g()
2989 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168g()
2990 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168g()
2992 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168g()
2995 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)  in rtl_hw_start_8168g_1()  argument
3004 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_1()
3007 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168g_1()
3008 	rtl_ephy_init(tp, e_info_8168g_1);  in rtl_hw_start_8168g_1()
3009 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168g_1()
3012 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)  in rtl_hw_start_8168g_2()  argument
3026 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_2()
3029 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168g_2()
3030 	rtl_ephy_init(tp, e_info_8168g_2);  in rtl_hw_start_8168g_2()
3033 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)  in rtl_hw_start_8411_2()  argument
3048 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8411_2()
3051 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8411_2()
3052 	rtl_ephy_init(tp, e_info_8411_2);  in rtl_hw_start_8411_2()
3057 	r8168_mac_ocp_write(tp, 0xFC28, 0x0000);  in rtl_hw_start_8411_2()
3058 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);  in rtl_hw_start_8411_2()
3059 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);  in rtl_hw_start_8411_2()
3060 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);  in rtl_hw_start_8411_2()
3061 	r8168_mac_ocp_write(tp, 0xFC30, 0x0000);  in rtl_hw_start_8411_2()
3062 	r8168_mac_ocp_write(tp, 0xFC32, 0x0000);  in rtl_hw_start_8411_2()
3063 	r8168_mac_ocp_write(tp, 0xFC34, 0x0000);  in rtl_hw_start_8411_2()
3064 	r8168_mac_ocp_write(tp, 0xFC36, 0x0000);  in rtl_hw_start_8411_2()
3066 	r8168_mac_ocp_write(tp, 0xFC26, 0x0000);  in rtl_hw_start_8411_2()
3068 	r8168_mac_ocp_write(tp, 0xF800, 0xE008);  in rtl_hw_start_8411_2()
3069 	r8168_mac_ocp_write(tp, 0xF802, 0xE00A);  in rtl_hw_start_8411_2()
3070 	r8168_mac_ocp_write(tp, 0xF804, 0xE00C);  in rtl_hw_start_8411_2()
3071 	r8168_mac_ocp_write(tp, 0xF806, 0xE00E);  in rtl_hw_start_8411_2()
3072 	r8168_mac_ocp_write(tp, 0xF808, 0xE027);  in rtl_hw_start_8411_2()
3073 	r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);  in rtl_hw_start_8411_2()
3074 	r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);  in rtl_hw_start_8411_2()
3075 	r8168_mac_ocp_write(tp, 0xF80E, 0xE065);  in rtl_hw_start_8411_2()
3076 	r8168_mac_ocp_write(tp, 0xF810, 0xC602);  in rtl_hw_start_8411_2()
3077 	r8168_mac_ocp_write(tp, 0xF812, 0xBE00);  in rtl_hw_start_8411_2()
3078 	r8168_mac_ocp_write(tp, 0xF814, 0x0000);  in rtl_hw_start_8411_2()
3079 	r8168_mac_ocp_write(tp, 0xF816, 0xC502);  in rtl_hw_start_8411_2()
3080 	r8168_mac_ocp_write(tp, 0xF818, 0xBD00);  in rtl_hw_start_8411_2()
3081 	r8168_mac_ocp_write(tp, 0xF81A, 0x074C);  in rtl_hw_start_8411_2()
3082 	r8168_mac_ocp_write(tp, 0xF81C, 0xC302);  in rtl_hw_start_8411_2()
3083 	r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);  in rtl_hw_start_8411_2()
3084 	r8168_mac_ocp_write(tp, 0xF820, 0x080A);  in rtl_hw_start_8411_2()
3085 	r8168_mac_ocp_write(tp, 0xF822, 0x6420);  in rtl_hw_start_8411_2()
3086 	r8168_mac_ocp_write(tp, 0xF824, 0x48C2);  in rtl_hw_start_8411_2()
3087 	r8168_mac_ocp_write(tp, 0xF826, 0x8C20);  in rtl_hw_start_8411_2()
3088 	r8168_mac_ocp_write(tp, 0xF828, 0xC516);  in rtl_hw_start_8411_2()
3089 	r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);  in rtl_hw_start_8411_2()
3090 	r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);  in rtl_hw_start_8411_2()
3091 	r8168_mac_ocp_write(tp, 0xF82E, 0xF009);  in rtl_hw_start_8411_2()
3092 	r8168_mac_ocp_write(tp, 0xF830, 0x74A2);  in rtl_hw_start_8411_2()
3093 	r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);  in rtl_hw_start_8411_2()
3094 	r8168_mac_ocp_write(tp, 0xF834, 0x74A0);  in rtl_hw_start_8411_2()
3095 	r8168_mac_ocp_write(tp, 0xF836, 0xC50E);  in rtl_hw_start_8411_2()
3096 	r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);  in rtl_hw_start_8411_2()
3097 	r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);  in rtl_hw_start_8411_2()
3098 	r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);  in rtl_hw_start_8411_2()
3099 	r8168_mac_ocp_write(tp, 0xF83E, 0xE006);  in rtl_hw_start_8411_2()
3100 	r8168_mac_ocp_write(tp, 0xF840, 0x74F8);  in rtl_hw_start_8411_2()
3101 	r8168_mac_ocp_write(tp, 0xF842, 0x48C4);  in rtl_hw_start_8411_2()
3102 	r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);  in rtl_hw_start_8411_2()
3103 	r8168_mac_ocp_write(tp, 0xF846, 0xC404);  in rtl_hw_start_8411_2()
3104 	r8168_mac_ocp_write(tp, 0xF848, 0xBC00);  in rtl_hw_start_8411_2()
3105 	r8168_mac_ocp_write(tp, 0xF84A, 0xC403);  in rtl_hw_start_8411_2()
3106 	r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);  in rtl_hw_start_8411_2()
3107 	r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);  in rtl_hw_start_8411_2()
3108 	r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);  in rtl_hw_start_8411_2()
3109 	r8168_mac_ocp_write(tp, 0xF852, 0xE434);  in rtl_hw_start_8411_2()
3110 	r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);  in rtl_hw_start_8411_2()
3111 	r8168_mac_ocp_write(tp, 0xF856, 0x49D9);  in rtl_hw_start_8411_2()
3112 	r8168_mac_ocp_write(tp, 0xF858, 0xF01F);  in rtl_hw_start_8411_2()
3113 	r8168_mac_ocp_write(tp, 0xF85A, 0xC526);  in rtl_hw_start_8411_2()
3114 	r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);  in rtl_hw_start_8411_2()
3115 	r8168_mac_ocp_write(tp, 0xF85E, 0x1400);  in rtl_hw_start_8411_2()
3116 	r8168_mac_ocp_write(tp, 0xF860, 0xF007);  in rtl_hw_start_8411_2()
3117 	r8168_mac_ocp_write(tp, 0xF862, 0x0C01);  in rtl_hw_start_8411_2()
3118 	r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);  in rtl_hw_start_8411_2()
3119 	r8168_mac_ocp_write(tp, 0xF866, 0x1C15);  in rtl_hw_start_8411_2()
3120 	r8168_mac_ocp_write(tp, 0xF868, 0xC51B);  in rtl_hw_start_8411_2()
3121 	r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);  in rtl_hw_start_8411_2()
3122 	r8168_mac_ocp_write(tp, 0xF86C, 0xE013);  in rtl_hw_start_8411_2()
3123 	r8168_mac_ocp_write(tp, 0xF86E, 0xC519);  in rtl_hw_start_8411_2()
3124 	r8168_mac_ocp_write(tp, 0xF870, 0x74A0);  in rtl_hw_start_8411_2()
3125 	r8168_mac_ocp_write(tp, 0xF872, 0x48C4);  in rtl_hw_start_8411_2()
3126 	r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);  in rtl_hw_start_8411_2()
3127 	r8168_mac_ocp_write(tp, 0xF876, 0xC516);  in rtl_hw_start_8411_2()
3128 	r8168_mac_ocp_write(tp, 0xF878, 0x74A4);  in rtl_hw_start_8411_2()
3129 	r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);  in rtl_hw_start_8411_2()
3130 	r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);  in rtl_hw_start_8411_2()
3131 	r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);  in rtl_hw_start_8411_2()
3132 	r8168_mac_ocp_write(tp, 0xF880, 0xC512);  in rtl_hw_start_8411_2()
3133 	r8168_mac_ocp_write(tp, 0xF882, 0x1B00);  in rtl_hw_start_8411_2()
3134 	r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);  in rtl_hw_start_8411_2()
3135 	r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);  in rtl_hw_start_8411_2()
3136 	r8168_mac_ocp_write(tp, 0xF888, 0x483F);  in rtl_hw_start_8411_2()
3137 	r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);  in rtl_hw_start_8411_2()
3138 	r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);  in rtl_hw_start_8411_2()
3139 	r8168_mac_ocp_write(tp, 0xF88E, 0xC508);  in rtl_hw_start_8411_2()
3140 	r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);  in rtl_hw_start_8411_2()
3141 	r8168_mac_ocp_write(tp, 0xF892, 0xC505);  in rtl_hw_start_8411_2()
3142 	r8168_mac_ocp_write(tp, 0xF894, 0xBD00);  in rtl_hw_start_8411_2()
3143 	r8168_mac_ocp_write(tp, 0xF896, 0xC502);  in rtl_hw_start_8411_2()
3144 	r8168_mac_ocp_write(tp, 0xF898, 0xBD00);  in rtl_hw_start_8411_2()
3145 	r8168_mac_ocp_write(tp, 0xF89A, 0x0300);  in rtl_hw_start_8411_2()
3146 	r8168_mac_ocp_write(tp, 0xF89C, 0x051E);  in rtl_hw_start_8411_2()
3147 	r8168_mac_ocp_write(tp, 0xF89E, 0xE434);  in rtl_hw_start_8411_2()
3148 	r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);  in rtl_hw_start_8411_2()
3149 	r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);  in rtl_hw_start_8411_2()
3150 	r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);  in rtl_hw_start_8411_2()
3151 	r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);  in rtl_hw_start_8411_2()
3152 	r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);  in rtl_hw_start_8411_2()
3153 	r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);  in rtl_hw_start_8411_2()
3154 	r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);  in rtl_hw_start_8411_2()
3155 	r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);  in rtl_hw_start_8411_2()
3156 	r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);  in rtl_hw_start_8411_2()
3157 	r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);  in rtl_hw_start_8411_2()
3158 	r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);  in rtl_hw_start_8411_2()
3159 	r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);  in rtl_hw_start_8411_2()
3160 	r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);  in rtl_hw_start_8411_2()
3161 	r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);  in rtl_hw_start_8411_2()
3162 	r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);  in rtl_hw_start_8411_2()
3163 	r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);  in rtl_hw_start_8411_2()
3164 	r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);  in rtl_hw_start_8411_2()
3165 	r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);  in rtl_hw_start_8411_2()
3166 	r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);  in rtl_hw_start_8411_2()
3167 	r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);  in rtl_hw_start_8411_2()
3168 	r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);  in rtl_hw_start_8411_2()
3169 	r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);  in rtl_hw_start_8411_2()
3170 	r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);  in rtl_hw_start_8411_2()
3171 	r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);  in rtl_hw_start_8411_2()
3172 	r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);  in rtl_hw_start_8411_2()
3173 	r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);  in rtl_hw_start_8411_2()
3174 	r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);  in rtl_hw_start_8411_2()
3175 	r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);  in rtl_hw_start_8411_2()
3176 	r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);  in rtl_hw_start_8411_2()
3177 	r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);  in rtl_hw_start_8411_2()
3178 	r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);  in rtl_hw_start_8411_2()
3180 	r8168_mac_ocp_write(tp, 0xFC26, 0x8000);  in rtl_hw_start_8411_2()
3182 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);  in rtl_hw_start_8411_2()
3183 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);  in rtl_hw_start_8411_2()
3184 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);  in rtl_hw_start_8411_2()
3185 	r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);  in rtl_hw_start_8411_2()
3186 	r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);  in rtl_hw_start_8411_2()
3187 	r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);  in rtl_hw_start_8411_2()
3188 	r8168_mac_ocp_write(tp, 0xFC36, 0x012D);  in rtl_hw_start_8411_2()
3190 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8411_2()
3193 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)  in rtl_hw_start_8168h_1()  argument
3206 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168h_1()
3207 	rtl_ephy_init(tp, e_info_8168h_1);  in rtl_hw_start_8168h_1()
3209 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168h_1()
3210 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168h_1()
3212 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168h_1()
3214 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168h_1()
3216 	rtl_eri_set_bits(tp, 0xd4, 0x1f00);  in rtl_hw_start_8168h_1()
3217 	rtl_eri_set_bits(tp, 0xdc, 0x001c);  in rtl_hw_start_8168h_1()
3219 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168h_1()
3221 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168h_1()
3223 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3224 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3226 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168h_1()
3228 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168h_1()
3229 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168h_1()
3231 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168h_1()
3233 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168h_1()
3235 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168h_1()
3237 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8168h_1()
3243 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8168h_1()
3246 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8168h_1()
3247 	r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);  in rtl_hw_start_8168h_1()
3248 	r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);  in rtl_hw_start_8168h_1()
3249 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8168h_1()
3251 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8168h_1()
3252 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8168h_1()
3253 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8168h_1()
3254 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8168h_1()
3256 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168h_1()
3259 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)  in rtl_hw_start_8168ep()  argument
3261 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8168ep()
3263 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168ep()
3264 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8168ep()
3266 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168ep()
3268 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168ep()
3270 	rtl_eri_set_bits(tp, 0xd4, 0x1f80);  in rtl_hw_start_8168ep()
3272 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168ep()
3274 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168ep()
3276 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3277 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3279 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168ep()
3281 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168ep()
3283 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168ep()
3285 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168ep()
3288 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_1()  argument
3299 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168ep_1()
3300 	rtl_ephy_init(tp, e_info_8168ep_1);  in rtl_hw_start_8168ep_1()
3302 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_1()
3304 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168ep_1()
3307 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_2()  argument
3316 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168ep_2()
3317 	rtl_ephy_init(tp, e_info_8168ep_2);  in rtl_hw_start_8168ep_2()
3319 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_2()
3321 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168ep_2()
3322 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168ep_2()
3324 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168ep_2()
3327 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_3()  argument
3337 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168ep_3()
3338 	rtl_ephy_init(tp, e_info_8168ep_3);  in rtl_hw_start_8168ep_3()
3340 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_3()
3342 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168ep_3()
3343 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168ep_3()
3345 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);  in rtl_hw_start_8168ep_3()
3346 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8168ep_3()
3347 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8168ep_3()
3349 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168ep_3()
3352 static void rtl_hw_start_8117(struct rtl8169_private *tp)  in rtl_hw_start_8117()  argument
3360 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8117()
3363 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8117()
3364 	rtl_ephy_init(tp, e_info_8117);  in rtl_hw_start_8117()
3366 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8117()
3367 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8117()
3369 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8117()
3371 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8117()
3373 	rtl_eri_set_bits(tp, 0xd4, 0x1f90);  in rtl_hw_start_8117()
3375 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8117()
3377 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8117()
3379 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3380 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3382 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8117()
3384 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8117()
3385 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8117()
3387 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8117()
3389 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8117()
3391 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8117()
3393 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8117()
3398 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8117()
3401 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8117()
3402 	r8168_mac_ocp_write(tp, 0xea80, 0x0003);  in rtl_hw_start_8117()
3403 	r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);  in rtl_hw_start_8117()
3404 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8117()
3406 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8117()
3407 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8117()
3408 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8117()
3409 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8117()
3412 	r8169_apply_firmware(tp);  in rtl_hw_start_8117()
3414 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8117()
3417 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)  in rtl_hw_start_8102e_1()  argument
3431 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_1()
3433 	RTL_W8(tp, DBG_REG, FIX_NAK_1);  in rtl_hw_start_8102e_1()
3435 	RTL_W8(tp, Config1,  in rtl_hw_start_8102e_1()
3437 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_1()
3439 	cfg1 = RTL_R8(tp, Config1);  in rtl_hw_start_8102e_1()
3441 		RTL_W8(tp, Config1, cfg1 & ~LEDS0);  in rtl_hw_start_8102e_1()
3443 	rtl_ephy_init(tp, e_info_8102e_1);  in rtl_hw_start_8102e_1()
3446 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)  in rtl_hw_start_8102e_2()  argument
3448 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_2()
3450 	RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);  in rtl_hw_start_8102e_2()
3451 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_2()
3454 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)  in rtl_hw_start_8102e_3()  argument
3456 	rtl_hw_start_8102e_2(tp);  in rtl_hw_start_8102e_3()
3458 	rtl_ephy_write(tp, 0x03, 0xc2f9);  in rtl_hw_start_8102e_3()
3461 static void rtl_hw_start_8401(struct rtl8169_private *tp)  in rtl_hw_start_8401()  argument
3470 	rtl_ephy_init(tp, e_info_8401);  in rtl_hw_start_8401()
3471 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8401()
3474 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)  in rtl_hw_start_8105e_1()  argument
3488 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8105e_1()
3491 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);  in rtl_hw_start_8105e_1()
3493 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8105e_1()
3494 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8105e_1()
3496 	rtl_ephy_init(tp, e_info_8105e_1);  in rtl_hw_start_8105e_1()
3498 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8105e_1()
3501 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)  in rtl_hw_start_8105e_2()  argument
3503 	rtl_hw_start_8105e_1(tp);  in rtl_hw_start_8105e_2()
3504 	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);  in rtl_hw_start_8105e_2()
3507 static void rtl_hw_start_8402(struct rtl8169_private *tp)  in rtl_hw_start_8402()  argument
3514 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8402()
3517 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8402()
3519 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8402()
3521 	rtl_ephy_init(tp, e_info_8402);  in rtl_hw_start_8402()
3523 	rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);  in rtl_hw_start_8402()
3524 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8402()
3525 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3526 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3527 	rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);  in rtl_hw_start_8402()
3530 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3532 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8402()
3535 static void rtl_hw_start_8106(struct rtl8169_private *tp)  in rtl_hw_start_8106()  argument
3537 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8106()
3540 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8106()
3542 	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);  in rtl_hw_start_8106()
3543 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8106()
3544 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8106()
3546 	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3549 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3551 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8106()
3552 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8106()
3557 	return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);  in DECLARE_RTL_COND()
3560 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)  in rtl_hw_start_8125_common()  argument
3562 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8125_common()
3564 	RTL_W16(tp, 0x382, 0x221b);  in rtl_hw_start_8125_common()
3565 	RTL_W8(tp, 0x4500, 0);  in rtl_hw_start_8125_common()
3566 	RTL_W16(tp, 0x4800, 0);  in rtl_hw_start_8125_common()
3569 	r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);  in rtl_hw_start_8125_common()
3571 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);  in rtl_hw_start_8125_common()
3573 	r8168_mac_ocp_write(tp, 0xc140, 0xffff);  in rtl_hw_start_8125_common()
3574 	r8168_mac_ocp_write(tp, 0xc142, 0xffff);  in rtl_hw_start_8125_common()
3576 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);  in rtl_hw_start_8125_common()
3577 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8125_common()
3578 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8125_common()
3581 	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3583 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3584 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);  in rtl_hw_start_8125_common()
3586 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);  in rtl_hw_start_8125_common()
3588 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3589 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);  in rtl_hw_start_8125_common()
3591 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);  in rtl_hw_start_8125_common()
3593 	r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);  in rtl_hw_start_8125_common()
3594 	r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);  in rtl_hw_start_8125_common()
3595 	r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);  in rtl_hw_start_8125_common()
3596 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);  in rtl_hw_start_8125_common()
3597 	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);  in rtl_hw_start_8125_common()
3598 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);  in rtl_hw_start_8125_common()
3599 	r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);  in rtl_hw_start_8125_common()
3600 	r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);  in rtl_hw_start_8125_common()
3601 	r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);  in rtl_hw_start_8125_common()
3602 	r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);  in rtl_hw_start_8125_common()
3604 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);  in rtl_hw_start_8125_common()
3605 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);  in rtl_hw_start_8125_common()
3607 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3608 	RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);  in rtl_hw_start_8125_common()
3610 	r8168_mac_ocp_write(tp, 0xe098, 0xc302);  in rtl_hw_start_8125_common()
3612 	rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);  in rtl_hw_start_8125_common()
3614 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3615 		rtl8125b_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3617 		rtl8125a_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3619 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8125_common()
3623 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)  in rtl_hw_start_8125a_1()  argument
3653 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125a_1()
3656 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8125a_1()
3657 	rtl_ephy_init(tp, e_info_8125a_1);  in rtl_hw_start_8125a_1()
3659 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125a_1()
3660 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8125a_1()
3663 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)  in rtl_hw_start_8125a_2()  argument
3681 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125a_2()
3684 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8125a_2()
3685 	rtl_ephy_init(tp, e_info_8125a_2);  in rtl_hw_start_8125a_2()
3687 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125a_2()
3688 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8125a_2()
3691 static void rtl_hw_start_8125b(struct rtl8169_private *tp)  in rtl_hw_start_8125b()  argument
3702 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125b()
3703 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8125b()
3705 	rtl_ephy_init(tp, e_info_8125b);  in rtl_hw_start_8125b()
3706 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125b()
3708 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8125b()
3711 static void rtl_hw_config(struct rtl8169_private *tp)  in rtl_hw_config()  argument
3764 	if (hw_configs[tp->mac_version])  in rtl_hw_config()
3765 		hw_configs[tp->mac_version](tp);  in rtl_hw_config()
3768 static void rtl_hw_start_8125(struct rtl8169_private *tp)  in rtl_hw_start_8125()  argument
3774 		RTL_W32(tp, i, 0);  in rtl_hw_start_8125()
3776 	rtl_hw_config(tp);  in rtl_hw_start_8125()
3779 static void rtl_hw_start_8168(struct rtl8169_private *tp)  in rtl_hw_start_8168()  argument
3781 	if (rtl_is_8168evl_up(tp))  in rtl_hw_start_8168()
3782 		RTL_W8(tp, MaxTxPacketSize, EarlySize);  in rtl_hw_start_8168()
3784 		RTL_W8(tp, MaxTxPacketSize, TxPacketMax);  in rtl_hw_start_8168()
3786 	rtl_hw_config(tp);  in rtl_hw_start_8168()
3789 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8168()
3792 static void rtl_hw_start_8169(struct rtl8169_private *tp)  in rtl_hw_start_8169()  argument
3794 	RTL_W8(tp, EarlyTxThres, NoEarlyTx);  in rtl_hw_start_8169()
3796 	tp->cp_cmd |= PCIMulRW;  in rtl_hw_start_8169()
3798 	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||  in rtl_hw_start_8169()
3799 	    tp->mac_version == RTL_GIGA_MAC_VER_03)  in rtl_hw_start_8169()
3800 		tp->cp_cmd |= EnAnaPLL;  in rtl_hw_start_8169()
3802 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start_8169()
3804 	rtl8169_set_magic_reg(tp);  in rtl_hw_start_8169()
3807 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8169()
3810 static void rtl_hw_start(struct  rtl8169_private *tp)  in rtl_hw_start()  argument
3812 	rtl_unlock_config_regs(tp);  in rtl_hw_start()
3814 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start()
3816 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_hw_start()
3817 		rtl_hw_start_8169(tp);  in rtl_hw_start()
3818 	else if (rtl_is_8125(tp))  in rtl_hw_start()
3819 		rtl_hw_start_8125(tp);  in rtl_hw_start()
3821 		rtl_hw_start_8168(tp);  in rtl_hw_start()
3823 	rtl_set_rx_max_size(tp);  in rtl_hw_start()
3824 	rtl_set_rx_tx_desc_registers(tp);  in rtl_hw_start()
3825 	rtl_lock_config_regs(tp);  in rtl_hw_start()
3827 	rtl_jumbo_config(tp);  in rtl_hw_start()
3830 	rtl_pci_commit(tp);  in rtl_hw_start()
3832 	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);  in rtl_hw_start()
3833 	rtl_init_rxcfg(tp);  in rtl_hw_start()
3834 	rtl_set_tx_config_registers(tp);  in rtl_hw_start()
3835 	rtl_set_rx_config_features(tp, tp->dev->features);  in rtl_hw_start()
3836 	rtl_set_rx_mode(tp->dev);  in rtl_hw_start()
3837 	rtl_irq_enable(tp);  in rtl_hw_start()
3842 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_change_mtu()  local
3846 	rtl_jumbo_config(tp);  in rtl8169_change_mtu()
3848 	switch (tp->mac_version) {  in rtl8169_change_mtu()
3851 		rtl8125_set_eee_txidle_timer(tp);  in rtl8169_change_mtu()
3870 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,  in rtl8169_alloc_rx_data()  argument
3873 	struct device *d = tp_to_dev(tp);  in rtl8169_alloc_rx_data()
3884 		netdev_err(tp->dev, "Failed to map RX DMA!\n");  in rtl8169_alloc_rx_data()
3895 static void rtl8169_rx_clear(struct rtl8169_private *tp)  in rtl8169_rx_clear()  argument
3899 	for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {  in rtl8169_rx_clear()
3900 		dma_unmap_page(tp_to_dev(tp),  in rtl8169_rx_clear()
3901 			       le64_to_cpu(tp->RxDescArray[i].addr),  in rtl8169_rx_clear()
3903 		__free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));  in rtl8169_rx_clear()
3904 		tp->Rx_databuff[i] = NULL;  in rtl8169_rx_clear()
3905 		tp->RxDescArray[i].addr = 0;  in rtl8169_rx_clear()
3906 		tp->RxDescArray[i].opts1 = 0;  in rtl8169_rx_clear()
3910 static int rtl8169_rx_fill(struct rtl8169_private *tp)  in rtl8169_rx_fill()  argument
3917 		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);  in rtl8169_rx_fill()
3919 			rtl8169_rx_clear(tp);  in rtl8169_rx_fill()
3922 		tp->Rx_databuff[i] = data;  in rtl8169_rx_fill()
3926 	tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);  in rtl8169_rx_fill()
3931 static int rtl8169_init_ring(struct rtl8169_private *tp)  in rtl8169_init_ring()  argument
3933 	rtl8169_init_ring_indexes(tp);  in rtl8169_init_ring()
3935 	memset(tp->tx_skb, 0, sizeof(tp->tx_skb));  in rtl8169_init_ring()
3936 	memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));  in rtl8169_init_ring()
3938 	return rtl8169_rx_fill(tp);  in rtl8169_init_ring()
3941 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)  in rtl8169_unmap_tx_skb()  argument
3943 	struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_unmap_tx_skb()
3944 	struct TxDesc *desc = tp->TxDescArray + entry;  in rtl8169_unmap_tx_skb()
3946 	dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,  in rtl8169_unmap_tx_skb()
3952 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,  in rtl8169_tx_clear_range()  argument
3959 		struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_tx_clear_range()
3965 			rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_tx_clear_range()
3972 static void rtl8169_tx_clear(struct rtl8169_private *tp)  in rtl8169_tx_clear()  argument
3974 	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);  in rtl8169_tx_clear()
3975 	netdev_reset_queue(tp->dev);  in rtl8169_tx_clear()
3978 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)  in rtl8169_cleanup()  argument
3980 	napi_disable(&tp->napi);  in rtl8169_cleanup()
3986 	rtl8169_irq_mask_and_ack(tp);  in rtl8169_cleanup()
3988 	rtl_rx_close(tp);  in rtl8169_cleanup()
3990 	if (going_down && tp->dev->wol_enabled)  in rtl8169_cleanup()
3993 	switch (tp->mac_version) {  in rtl8169_cleanup()
3997 		rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);  in rtl8169_cleanup()
4000 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
4001 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);  in rtl8169_cleanup()
4004 		rtl_enable_rxdvgate(tp);  in rtl8169_cleanup()
4008 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
4013 	rtl_hw_reset(tp);  in rtl8169_cleanup()
4015 	rtl8169_tx_clear(tp);  in rtl8169_cleanup()
4016 	rtl8169_init_ring_indexes(tp);  in rtl8169_cleanup()
4019 static void rtl_reset_work(struct rtl8169_private *tp)  in rtl_reset_work()  argument
4023 	netif_stop_queue(tp->dev);  in rtl_reset_work()
4025 	rtl8169_cleanup(tp, false);  in rtl_reset_work()
4028 		rtl8169_mark_to_asic(tp->RxDescArray + i);  in rtl_reset_work()
4030 	napi_enable(&tp->napi);  in rtl_reset_work()
4031 	rtl_hw_start(tp);  in rtl_reset_work()
4036 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_tx_timeout()  local
4038 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_tx_timeout()
4041 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,  in rtl8169_tx_map()  argument
4044 	struct TxDesc *txd = tp->TxDescArray + entry;  in rtl8169_tx_map()
4045 	struct device *d = tp_to_dev(tp);  in rtl8169_tx_map()
4054 			netdev_err(tp->dev, "Failed to map TX data!\n");  in rtl8169_tx_map()
4068 	tp->tx_skb[entry].len = len;  in rtl8169_tx_map()
4073 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,  in rtl8169_xmit_frags()  argument
4086 		if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))  in rtl8169_xmit_frags()
4093 	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);  in rtl8169_xmit_frags()
4118 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,  in rtl8125_quirk_udp_padto()  argument
4123 	if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&  in rtl8125_quirk_udp_padto()
4145 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,  in rtl_quirk_packet_padto()  argument
4150 	padto = rtl8125_quirk_udp_padto(tp, skb);  in rtl_quirk_packet_padto()
4152 	switch (tp->mac_version) {  in rtl_quirk_packet_padto()
4184 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,  in rtl8169_tso_csum_v2()  argument
4233 		unsigned int padto = rtl_quirk_packet_padto(tp, skb);  in rtl8169_tso_csum_v2()
4242 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,  in rtl_tx_slots_avail()  argument
4245 	unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;  in rtl_tx_slots_avail()
4252 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)  in rtl_chip_supports_csum_v2()  argument
4254 	switch (tp->mac_version) {  in rtl_chip_supports_csum_v2()
4263 static void rtl8169_doorbell(struct rtl8169_private *tp)  in rtl8169_doorbell()  argument
4265 	if (rtl_is_8125(tp))  in rtl8169_doorbell()
4266 		RTL_W16(tp, TxPoll_8125, BIT(0));  in rtl8169_doorbell()
4268 		RTL_W8(tp, TxPoll, NPQ);  in rtl8169_doorbell()
4275 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_start_xmit()  local
4276 	unsigned int entry = tp->cur_tx % NUM_TX_DESC;  in rtl8169_start_xmit()
4281 	txd_first = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4283 	if (unlikely(!rtl_tx_slots_avail(tp, frags))) {  in rtl8169_start_xmit()
4295 	if (!rtl_chip_supports_csum_v2(tp))  in rtl8169_start_xmit()
4297 	else if (!rtl8169_tso_csum_v2(tp, skb, opts))  in rtl8169_start_xmit()
4300 	if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,  in rtl8169_start_xmit()
4305 		if (rtl8169_xmit_frags(tp, skb, opts, entry))  in rtl8169_start_xmit()
4310 	txd_last = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4312 	tp->tx_skb[entry].skb = skb;  in rtl8169_start_xmit()
4326 	tp->cur_tx += frags + 1;  in rtl8169_start_xmit()
4328 	stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);  in rtl8169_start_xmit()
4339 		rtl8169_doorbell(tp);  in rtl8169_start_xmit()
4350 		if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))  in rtl8169_start_xmit()
4357 	rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_start_xmit()
4404 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_features_check()  local
4407 		if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl8169_features_check()
4411 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4418 		if (rtl_quirk_packet_padto(tp, skb))  in rtl8169_features_check()
4422 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4431 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_pcierr_interrupt()  local
4432 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_pcierr_interrupt()
4458 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_pcierr_interrupt()
4461 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,  in rtl_tx()  argument
4466 	dirty_tx = tp->dirty_tx;  in rtl_tx()
4469 	for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {  in rtl_tx()
4471 		struct sk_buff *skb = tp->tx_skb[entry].skb;  in rtl_tx()
4474 		status = le32_to_cpu(tp->TxDescArray[entry].opts1);  in rtl_tx()
4478 		rtl8169_unmap_tx_skb(tp, entry);  in rtl_tx()
4488 	if (tp->dirty_tx != dirty_tx) {  in rtl_tx()
4491 		rtl_inc_priv_stats(&tp->tx_stats, pkts_compl, bytes_compl);  in rtl_tx()
4493 		tp->dirty_tx = dirty_tx;  in rtl_tx()
4503 		    rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {  in rtl_tx()
4512 		if (tp->cur_tx != dirty_tx)  in rtl_tx()
4513 			rtl8169_doorbell(tp);  in rtl_tx()
4533 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)  in rtl_rx()  argument
4536 	struct device *d = tp_to_dev(tp);  in rtl_rx()
4538 	cur_rx = tp->cur_rx;  in rtl_rx()
4542 		struct RxDesc *desc = tp->RxDescArray + entry;  in rtl_rx()
4587 		skb = napi_alloc_skb(&tp->napi, pkt_size);  in rtl_rx()
4594 		rx_buf = page_address(tp->Rx_databuff[entry]);  in rtl_rx()
4611 		napi_gro_receive(&tp->napi, skb);  in rtl_rx()
4613 		rtl_inc_priv_stats(&tp->rx_stats, 1, pkt_size);  in rtl_rx()
4618 	count = cur_rx - tp->cur_rx;  in rtl_rx()
4619 	tp->cur_rx = cur_rx;  in rtl_rx()
4626 	struct rtl8169_private *tp = dev_instance;  in rtl8169_interrupt()  local
4627 	u32 status = rtl_get_events(tp);  in rtl8169_interrupt()
4629 	if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))  in rtl8169_interrupt()
4633 		rtl8169_pcierr_interrupt(tp->dev);  in rtl8169_interrupt()
4638 		phy_mac_interrupt(tp->phydev);  in rtl8169_interrupt()
4641 	    tp->mac_version == RTL_GIGA_MAC_VER_11)) {  in rtl8169_interrupt()
4642 		netif_stop_queue(tp->dev);  in rtl8169_interrupt()
4643 		rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_interrupt()
4646 	rtl_irq_disable(tp);  in rtl8169_interrupt()
4647 	napi_schedule(&tp->napi);  in rtl8169_interrupt()
4649 	rtl_ack_events(tp, status);  in rtl8169_interrupt()
4656 	struct rtl8169_private *tp =  in rtl_task()  local
4661 	if (!netif_running(tp->dev) ||  in rtl_task()
4662 	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))  in rtl_task()
4665 	if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {  in rtl_task()
4666 		rtl_reset_work(tp);  in rtl_task()
4667 		netif_wake_queue(tp->dev);  in rtl_task()
4675 	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);  in rtl8169_poll()  local
4676 	struct net_device *dev = tp->dev;  in rtl8169_poll()
4679 	work_done = rtl_rx(dev, tp, (u32) budget);  in rtl8169_poll()
4681 	rtl_tx(dev, tp, budget);  in rtl8169_poll()
4684 		rtl_irq_enable(tp);  in rtl8169_poll()
4691 	struct rtl8169_private *tp = netdev_priv(ndev);  in r8169_phylink_handler()  local
4694 		rtl_link_chg_patch(tp);  in r8169_phylink_handler()
4695 		pm_request_resume(&tp->pci_dev->dev);  in r8169_phylink_handler()
4697 		pm_runtime_idle(&tp->pci_dev->dev);  in r8169_phylink_handler()
4701 		phy_print_status(tp->phydev);  in r8169_phylink_handler()
4704 static int r8169_phy_connect(struct rtl8169_private *tp)  in r8169_phy_connect()  argument
4706 	struct phy_device *phydev = tp->phydev;  in r8169_phy_connect()
4710 	phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :  in r8169_phy_connect()
4713 	ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,  in r8169_phy_connect()
4718 	if (!tp->supports_gmii)  in r8169_phy_connect()
4726 static void rtl8169_down(struct rtl8169_private *tp)  in rtl8169_down()  argument
4729 	bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);  in rtl8169_down()
4731 	phy_stop(tp->phydev);  in rtl8169_down()
4733 	rtl8169_update_counters(tp);  in rtl8169_down()
4735 	pci_clear_master(tp->pci_dev);  in rtl8169_down()
4736 	rtl_pci_commit(tp);  in rtl8169_down()
4738 	rtl8169_cleanup(tp, true);  in rtl8169_down()
4740 	rtl_pll_power_down(tp);  in rtl8169_down()
4743 static void rtl8169_up(struct rtl8169_private *tp)  in rtl8169_up()  argument
4745 	pci_set_master(tp->pci_dev);  in rtl8169_up()
4746 	rtl_pll_power_up(tp);  in rtl8169_up()
4747 	rtl8169_init_phy(tp);  in rtl8169_up()
4748 	napi_enable(&tp->napi);  in rtl8169_up()
4749 	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);  in rtl8169_up()
4750 	rtl_reset_work(tp);  in rtl8169_up()
4752 	phy_start(tp->phydev);  in rtl8169_up()
4757 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_close()  local
4758 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_close()
4763 	rtl8169_down(tp);  in rtl8169_close()
4764 	rtl8169_rx_clear(tp);  in rtl8169_close()
4766 	cancel_work_sync(&tp->wk.work);  in rtl8169_close()
4768 	free_irq(pci_irq_vector(pdev, 0), tp);  in rtl8169_close()
4770 	phy_disconnect(tp->phydev);  in rtl8169_close()
4772 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl8169_close()
4773 			  tp->RxPhyAddr);  in rtl8169_close()
4774 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl8169_close()
4775 			  tp->TxPhyAddr);  in rtl8169_close()
4776 	tp->TxDescArray = NULL;  in rtl8169_close()
4777 	tp->RxDescArray = NULL;  in rtl8169_close()
4787 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_netpoll()  local
4789 	rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);  in rtl8169_netpoll()
4795 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_open()  local
4796 	struct pci_dev *pdev = tp->pci_dev;  in rtl_open()
4805 	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,  in rtl_open()
4806 					     &tp->TxPhyAddr, GFP_KERNEL);  in rtl_open()
4807 	if (!tp->TxDescArray)  in rtl_open()
4810 	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,  in rtl_open()
4811 					     &tp->RxPhyAddr, GFP_KERNEL);  in rtl_open()
4812 	if (!tp->RxDescArray)  in rtl_open()
4815 	retval = rtl8169_init_ring(tp);  in rtl_open()
4819 	rtl_request_firmware(tp);  in rtl_open()
4822 			     IRQF_SHARED, dev->name, tp);  in rtl_open()
4826 	retval = r8169_phy_connect(tp);  in rtl_open()
4830 	rtl8169_up(tp);  in rtl_open()
4831 	rtl8169_init_counter_offsets(tp);  in rtl_open()
4839 	free_irq(pci_irq_vector(pdev, 0), tp);  in rtl_open()
4841 	rtl_release_firmware(tp);  in rtl_open()
4842 	rtl8169_rx_clear(tp);  in rtl_open()
4844 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl_open()
4845 			  tp->RxPhyAddr);  in rtl_open()
4846 	tp->RxDescArray = NULL;  in rtl_open()
4848 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl_open()
4849 			  tp->TxPhyAddr);  in rtl_open()
4850 	tp->TxDescArray = NULL;  in rtl_open()
4859 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_stats64()  local
4860 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_get_stats64()
4861 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_get_stats64()
4867 	rtl_get_priv_stats(&tp->rx_stats, &stats->rx_packets, &stats->rx_bytes);  in rtl8169_get_stats64()
4868 	rtl_get_priv_stats(&tp->tx_stats, &stats->tx_packets, &stats->tx_bytes);  in rtl8169_get_stats64()
4875 		rtl8169_update_counters(tp);  in rtl8169_get_stats64()
4882 		le64_to_cpu(tp->tc_offset.tx_errors);  in rtl8169_get_stats64()
4884 		le32_to_cpu(tp->tc_offset.tx_multi_collision);  in rtl8169_get_stats64()
4886 		le16_to_cpu(tp->tc_offset.tx_aborted);  in rtl8169_get_stats64()
4888 		le16_to_cpu(tp->tc_offset.rx_missed);  in rtl8169_get_stats64()
4893 static void rtl8169_net_suspend(struct rtl8169_private *tp)  in rtl8169_net_suspend()  argument
4895 	netif_device_detach(tp->dev);  in rtl8169_net_suspend()
4897 	if (netif_running(tp->dev))  in rtl8169_net_suspend()
4898 		rtl8169_down(tp);  in rtl8169_net_suspend()
4903 static int rtl8169_net_resume(struct rtl8169_private *tp)  in rtl8169_net_resume()  argument
4905 	rtl_rar_set(tp, tp->dev->dev_addr);  in rtl8169_net_resume()
4907 	if (tp->TxDescArray)  in rtl8169_net_resume()
4908 		rtl8169_up(tp);  in rtl8169_net_resume()
4910 	netif_device_attach(tp->dev);  in rtl8169_net_resume()
4917 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_suspend()  local
4920 	rtl8169_net_suspend(tp);  in rtl8169_suspend()
4921 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_suspend()
4922 		clk_disable_unprepare(tp->clk);  in rtl8169_suspend()
4930 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_resume()  local
4932 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_resume()
4933 		clk_prepare_enable(tp->clk);  in rtl8169_resume()
4936 	if (tp->mac_version == RTL_GIGA_MAC_VER_37)  in rtl8169_resume()
4937 		rtl_init_rxcfg(tp);  in rtl8169_resume()
4939 	return rtl8169_net_resume(tp);  in rtl8169_resume()
4944 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_suspend()  local
4946 	if (!tp->TxDescArray) {  in rtl8169_runtime_suspend()
4947 		netif_device_detach(tp->dev);  in rtl8169_runtime_suspend()
4952 	__rtl8169_set_wol(tp, WAKE_PHY);  in rtl8169_runtime_suspend()
4953 	rtl8169_net_suspend(tp);  in rtl8169_runtime_suspend()
4961 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_resume()  local
4963 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_runtime_resume()
4965 	return rtl8169_net_resume(tp);  in rtl8169_runtime_resume()
4970 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_idle()  local
4972 	if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))  in rtl8169_runtime_idle()
4986 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)  in rtl_wol_shutdown_quirk()  argument
4989 	switch (tp->mac_version) {  in rtl_wol_shutdown_quirk()
4993 		pci_clear_master(tp->pci_dev);  in rtl_wol_shutdown_quirk()
4995 		RTL_W8(tp, ChipCmd, CmdRxEnb);  in rtl_wol_shutdown_quirk()
4996 		rtl_pci_commit(tp);  in rtl_wol_shutdown_quirk()
5005 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_shutdown()  local
5008 	rtl8169_net_suspend(tp);  in rtl_shutdown()
5012 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_shutdown()
5015 		if (tp->saved_wolopts) {  in rtl_shutdown()
5016 			rtl_wol_suspend_quirk(tp);  in rtl_shutdown()
5017 			rtl_wol_shutdown_quirk(tp);  in rtl_shutdown()
5027 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_remove_one()  local
5032 	unregister_netdev(tp->dev);  in rtl_remove_one()
5034 	if (r8168_check_dash(tp))  in rtl_remove_one()
5035 		rtl8168_driver_stop(tp);  in rtl_remove_one()
5037 	rtl_release_firmware(tp);  in rtl_remove_one()
5040 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_remove_one()
5063 static void rtl_set_irq_mask(struct rtl8169_private *tp)  in rtl_set_irq_mask()  argument
5065 	tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;  in rtl_set_irq_mask()
5067 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_set_irq_mask()
5068 		tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;  in rtl_set_irq_mask()
5069 	else if (tp->mac_version == RTL_GIGA_MAC_VER_11)  in rtl_set_irq_mask()
5071 		tp->irq_mask |= RxFIFOOver;  in rtl_set_irq_mask()
5073 		tp->irq_mask |= RxOverflow;  in rtl_set_irq_mask()
5076 static int rtl_alloc_irq(struct rtl8169_private *tp)  in rtl_alloc_irq()  argument
5080 	switch (tp->mac_version) {  in rtl_alloc_irq()
5082 		rtl_unlock_config_regs(tp);  in rtl_alloc_irq()
5083 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);  in rtl_alloc_irq()
5084 		rtl_lock_config_regs(tp);  in rtl_alloc_irq()
5094 	return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);  in rtl_alloc_irq()
5097 static void rtl_read_mac_address(struct rtl8169_private *tp,  in rtl_read_mac_address()  argument
5101 	if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {  in rtl_read_mac_address()
5102 		u32 value = rtl_eri_read(tp, 0xe0);  in rtl_read_mac_address()
5109 		value = rtl_eri_read(tp, 0xe4);  in rtl_read_mac_address()
5112 	} else if (rtl_is_8125(tp)) {  in rtl_read_mac_address()
5113 		rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);  in rtl_read_mac_address()
5119 	return RTL_R8(tp, MCU) & LINK_LIST_RDY;  in DECLARE_RTL_COND()
5122 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)  in r8168g_wait_ll_share_fifo_ready()  argument
5124 	rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);  in r8168g_wait_ll_share_fifo_ready()
5129 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_read_reg()  local
5134 	return rtl_readphy(tp, phyreg);  in r8169_mdio_read_reg()
5140 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_write_reg()  local
5145 	rtl_writephy(tp, phyreg, val);  in r8169_mdio_write_reg()
5150 static int r8169_mdio_register(struct rtl8169_private *tp)  in r8169_mdio_register()  argument
5152 	struct pci_dev *pdev = tp->pci_dev;  in r8169_mdio_register()
5161 	new_bus->priv = tp;  in r8169_mdio_register()
5174 	tp->phydev = mdiobus_get_phy(new_bus, 0);  in r8169_mdio_register()
5175 	if (!tp->phydev) {  in r8169_mdio_register()
5177 	} else if (!tp->phydev->drv) {  in r8169_mdio_register()
5182 			tp->phydev->phy_id);  in r8169_mdio_register()
5187 	phy_suspend(tp->phydev);  in r8169_mdio_register()
5192 static void rtl_hw_init_8168g(struct rtl8169_private *tp)  in rtl_hw_init_8168g()  argument
5194 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8168g()
5196 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8168g()
5198 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8168g()
5200 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8168g()
5201 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5203 	r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));  in rtl_hw_init_8168g()
5204 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5207 static void rtl_hw_init_8125(struct rtl8169_private *tp)  in rtl_hw_init_8125()  argument
5209 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8125()
5211 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8125()
5213 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8125()
5215 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8125()
5216 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5218 	r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);  in rtl_hw_init_8125()
5219 	r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);  in rtl_hw_init_8125()
5220 	r8168_mac_ocp_write(tp, 0xc01e, 0x5555);  in rtl_hw_init_8125()
5221 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5224 static void rtl_hw_initialize(struct rtl8169_private *tp)  in rtl_hw_initialize()  argument
5226 	switch (tp->mac_version) {  in rtl_hw_initialize()
5228 		rtl8168ep_stop_cmac(tp);  in rtl_hw_initialize()
5231 		rtl_hw_init_8168g(tp);  in rtl_hw_initialize()
5234 		rtl_hw_init_8125(tp);  in rtl_hw_initialize()
5241 static int rtl_jumbo_max(struct rtl8169_private *tp)  in rtl_jumbo_max()  argument
5244 	if (!tp->supports_gmii)  in rtl_jumbo_max()
5247 	switch (tp->mac_version) {  in rtl_jumbo_max()
5269 static int rtl_get_ether_clk(struct rtl8169_private *tp)  in rtl_get_ether_clk()  argument
5271 	struct device *d = tp_to_dev(tp);  in rtl_get_ether_clk()
5284 		tp->clk = clk;  in rtl_get_ether_clk()
5295 static void rtl_init_mac_address(struct rtl8169_private *tp)  in rtl_init_mac_address()  argument
5297 	struct net_device *dev = tp->dev;  in rtl_init_mac_address()
5301 	rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);  in rtl_init_mac_address()
5305 	rtl_read_mac_address(tp, mac_addr);  in rtl_init_mac_address()
5309 	rtl_read_mac_from_reg(tp, mac_addr, MAC0);  in rtl_init_mac_address()
5314 	dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");  in rtl_init_mac_address()
5316 	rtl_rar_set(tp, mac_addr);  in rtl_init_mac_address()
5321 	struct rtl8169_private *tp;  in rtl_init_one()  local
5327 	dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));  in rtl_init_one()
5333 	tp = netdev_priv(dev);  in rtl_init_one()
5334 	tp->dev = dev;  in rtl_init_one()
5335 	tp->pci_dev = pdev;  in rtl_init_one()
5336 	tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;  in rtl_init_one()
5337 	tp->eee_adv = -1;  in rtl_init_one()
5338 	tp->ocp_base = OCP_STD_PHY_BASE;  in rtl_init_one()
5341 	rc = rtl_get_ether_clk(tp);  in rtl_init_one()
5350 	tp->aspm_manageable = !rc;  in rtl_init_one()
5381 	tp->mmio_addr = pcim_iomap_table(pdev)[region];  in rtl_init_one()
5383 	xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;  in rtl_init_one()
5386 	chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);  in rtl_init_one()
5392 	tp->mac_version = chipset;  in rtl_init_one()
5394 	tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;  in rtl_init_one()
5396 	if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&  in rtl_init_one()
5400 	rtl_init_rxcfg(tp);  in rtl_init_one()
5402 	rtl8169_irq_mask_and_ack(tp);  in rtl_init_one()
5404 	rtl_hw_initialize(tp);  in rtl_init_one()
5406 	rtl_hw_reset(tp);  in rtl_init_one()
5408 	rc = rtl_alloc_irq(tp);  in rtl_init_one()
5414 	INIT_WORK(&tp->wk.work, rtl_task);  in rtl_init_one()
5415 	u64_stats_init(&tp->rx_stats.syncp);  in rtl_init_one()
5416 	u64_stats_init(&tp->tx_stats.syncp);  in rtl_init_one()
5418 	rtl_init_mac_address(tp);  in rtl_init_one()
5422 	netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);  in rtl_init_one()
5433 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl_init_one()
5437 	if (rtl_chip_supports_csum_v2(tp))  in rtl_init_one()
5447 	if (rtl_chip_supports_csum_v2(tp)) {  in rtl_init_one()
5463 	jumbo_max = rtl_jumbo_max(tp);  in rtl_init_one()
5467 	rtl_set_irq_mask(tp);  in rtl_init_one()
5469 	tp->fw_name = rtl_chip_infos[chipset].fw_name;  in rtl_init_one()
5471 	tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),  in rtl_init_one()
5472 					    &tp->counters_phys_addr,  in rtl_init_one()
5474 	if (!tp->counters)  in rtl_init_one()
5477 	pci_set_drvdata(pdev, tp);  in rtl_init_one()
5479 	rc = r8169_mdio_register(tp);  in rtl_init_one()
5484 	rtl_pll_power_down(tp);  in rtl_init_one()
5496 			    jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?  in rtl_init_one()
5499 	if (r8168_check_dash(tp)) {  in rtl_init_one()
5501 		rtl8168_driver_start(tp);  in rtl_init_one()