Lines Matching +full:0 +full:x3fffc000
49 #define device_set_wakeup_enable(dev, val) do {} while (0)
52 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
58 a[0] = b[0]; in ether_addr_copy()
64 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
66 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)
67 #define reinit_completion(x) ((x)->done = 0)
93 } while (0)
121 } while (0)
124 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0)
131 #endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0)
135 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0)
141 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
142 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
147 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,5,0)
159 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
164 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
174 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
177 #define IRQ_NONE 0
182 #define NETIF_F_RXALL 0
186 #define NETIF_F_RXFCS 0
211 #define PCI_VENDOR_ID_DLINK 0x1186
215 #define dma_mapping_error(a,b) 0
223 #define AUTONEG_DISABLE 0x00
227 #define AUTONEG_ENABLE 0x01
231 #define BMCR_SPEED1000 0x0040
235 #define BMCR_SPEED100 0x2000
239 #define BMCR_SPEED10 0x0000
247 #define DUPLEX_UNKNOWN 0xff
259 #define MDIO_EEE_100TX 0x0002
263 #define MDIO_EEE_1000T 0x0004
295 #define FALSE 0
303 #define false 0
358 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
360 #define assert(expr) do {} while (0)
361 #define dprintk(fmt, args...) do {} while (0)
389 #define NETIF_F_TSO6 0
401 #define TX_DMA_BURST_16 0
402 #define Reserved1_data 0x3F
403 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
413 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
414 #define RxEarly_off_V1 (0x07 << 11)
422 #define R8168_ERI_REGS_SIZE (0x100)
423 #define R8168_REGS_DUMP_SIZE (0x400)
424 #define R8168_PCI_REGS_SIZE (0x100)
434 #define RX_BUF_SIZE 0x05F3 /* 0x05F3 = 1522bye + 1 */
438 #define OCP_STD_PHY_BASE 0xa400
444 #define RTK_MAGIC_DEBUG_VALUE 0x0badbeef
455 #define DMA_64BIT_MASK 0xffffffffffffffffULL
459 #define DMA_32BIT_MASK 0x00000000ffffffffULL
463 #define NETDEV_TX_OK 0 /* driver took care of packet */
483 #define ADVERTISE_PAUSE_CAP 0x400
487 #define ADVERTISE_PAUSE_ASYM 0x800
491 #define MII_CTRL1000 0x09
495 #define ADVERTISE_1000FULL 0x200
499 #define ADVERTISE_1000HALF 0x100
510 (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \
551 #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
573 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0)
600 #define __chk_io_ptr(x) (void)0
646 /* 2.6.4 => 2.6.0 */
649 #endif /* 2.6.4 => 2.6.0 */
651 /* 2.6.0 => 2.5.28 */
652 #if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
672 return dma_addr == 0; in _kc_pci_dma_mapping_error()
679 #endif /* 2.6.0 => 2.5.28 */
688 /* 2.6.5 => 2.6.0 */
692 #endif /* 2.6.5 => 2.6.0 */
696 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
704 } while (0)
708 /* 2.6.4 => 2.6.0 */
711 (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
714 #endif /* 2.6.4 => 2.6.0 */
725 #define ETHTOOL_GSTATS 0x1d
745 u64 data[0];
750 #define ETHTOOL_PHYS_ID 0x1c
754 #define ETHTOOL_GSTRINGS 0x1b
756 ETH_SS_TEST = 0,
763 u8 data[0];
768 #define ETHTOOL_TEST 0x1a
770 ETH_TEST_FL_OFFLINE = (1 << 0),
778 u64 data[0];
783 #define ETHTOOL_GEEPROM 0xb
790 u8 data[0];
800 #define ETHTOOL_GLINK 0xa
804 #define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */
811 u8 data[0];
816 #define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */
819 #define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */
822 #define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */
825 #define ETHTOOL_GLINK 0x0000000a /* Get link status */
828 #define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */
831 #define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */
834 #define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */
841 * a packet arrives. If 0, only rx_max_coalesced_frames
847 * a packet arrives. If 0, only rx_coalesce_usecs is
863 * a packet is sent. If 0, only tx_max_coalesced_frames
869 * a packet is sent. If 0, only tx_coalesce_usecs is
934 #define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */
937 #define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */
963 #define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */
966 #define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */
989 #define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */
992 #define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */
995 #define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */
998 #define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */
1001 #define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */
1004 #define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable
1008 #define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable
1012 #define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */
1015 #define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */
1018 #define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */
1021 #define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */
1024 #define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */
1027 #define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */
1045 MAC0 = 0x00, /* Ethernet hardware address. */
1046 MAC4 = 0x04,
1047 MAR0 = 0x08, /* Multicast filter. */
1048 CounterAddrLow = 0x10,
1049 CounterAddrHigh = 0x14,
1050 CustomLED = 0x18,
1051 TxDescStartAddrLow = 0x20,
1052 TxDescStartAddrHigh = 0x24,
1053 TxHDescStartAddrLow = 0x28,
1054 TxHDescStartAddrHigh = 0x2c,
1055 FLASH = 0x30,
1056 ERSR = 0x36,
1057 ChipCmd = 0x37,
1058 TxPoll = 0x38,
1059 IntrMask = 0x3C,
1060 IntrStatus = 0x3E,
1061 TxConfig = 0x40,
1062 RxConfig = 0x44,
1063 TCTR = 0x48,
1064 Cfg9346 = 0x50,
1065 Config0 = 0x51,
1066 Config1 = 0x52,
1067 Config2 = 0x53,
1068 Config3 = 0x54,
1069 Config4 = 0x55,
1070 Config5 = 0x56,
1071 TDFNR = 0x57,
1072 TimeInt0 = 0x58,
1073 TimeInt1 = 0x5C,
1074 PHYAR = 0x60,
1075 CSIDR = 0x64,
1076 CSIAR = 0x68,
1077 PHYstatus = 0x6C,
1078 MACDBG = 0x6D,
1079 GPIO = 0x6E,
1080 PMCH = 0x6F,
1081 ERIDR = 0x70,
1082 ERIAR = 0x74,
1083 EPHY_RXER_NUM = 0x7C,
1084 EPHYAR = 0x80,
1085 TimeInt2 = 0x8C,
1086 OCPDR = 0xB0,
1087 MACOCP = 0xB0,
1088 OCPAR = 0xB4,
1089 SecMAC0 = 0xB4,
1090 SecMAC4 = 0xB8,
1091 PHYOCP = 0xB8,
1092 DBG_reg = 0xD1,
1093 TwiCmdReg = 0xD2,
1094 MCUCmd_reg = 0xD3,
1095 RxMaxSize = 0xDA,
1096 EFUSEAR = 0xDC,
1097 CPlusCmd = 0xE0,
1098 IntrMitigate = 0xE2,
1099 RxDescAddrLow = 0xE4,
1100 RxDescAddrHigh = 0xE8,
1101 MTPS = 0xEC,
1102 FuncEvent = 0xF0,
1103 PPSW = 0xF2,
1104 FuncEventMask = 0xF4,
1105 TimeInt3 = 0xF4,
1106 FuncPresetState = 0xF8,
1107 CMAC_IBCR0 = 0xF8,
1108 CMAC_IBCR2 = 0xF9,
1109 CMAC_IBIMR0 = 0xFA,
1110 CMAC_IBISR0 = 0xFB,
1111 FuncForceEvent = 0xFC,
1116 SYSErr = 0x8000,
1117 PCSTimeout = 0x4000,
1118 SWInt = 0x0100,
1119 TxDescUnavail = 0x0080,
1120 RxFIFOOver = 0x0040,
1121 LinkChg = 0x0020,
1122 RxDescUnavail = 0x0010,
1123 TxErr = 0x0008,
1124 TxOK = 0x0004,
1125 RxErr = 0x0002,
1126 RxOK = 0x0001,
1135 StopReq = 0x80,
1136 CmdReset = 0x10,
1137 CmdRxEnb = 0x08,
1138 CmdTxEnb = 0x04,
1139 RxBufEmpty = 0x01,
1142 Cfg9346_Lock = 0x00,
1143 Cfg9346_Unlock = 0xC0,
1144 Cfg9346_EEDO = (1 << 0),
1152 AcceptErr = 0x20,
1153 AcceptRunt = 0x10,
1154 AcceptBroadcast = 0x08,
1155 AcceptMulticast = 0x04,
1156 AcceptMyPhys = 0x02,
1157 AcceptAllPhys = 0x01,
1160 HPQ = 0x80,
1161 NPQ = 0x40,
1162 FSWInt = 0x01,
1174 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
1184 PMEnable = (1 << 0), /* Power Management Enable */
1198 Beacon_en = (1 << 0), /* This bit is reserved in RTL8168B*/
1208 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
1209 ASPM_en = (1 << 0), /* ASPM enable */
1223 Macdbgo_sel = 0x001C,
1224 INTT_0 = 0x0000,
1225 INTT_1 = 0x0001,
1226 INTT_2 = 0x0002,
1227 INTT_3 = 0x0003,
1230 PowerSaveStatus = 0x80,
1231 TxFlowCtrl = 0x40,
1232 RxFlowCtrl = 0x20,
1233 _1000bpsF = 0x10,
1234 _100bps = 0x08,
1235 _10bps = 0x04,
1236 LinkStatus = 0x02,
1237 FullDup = 0x01,
1242 DBGPIN_E2 = (1 << 0),
1245 CounterReset = 0x1,
1247 CounterDump = 0x8,
1250 PHYAR_Flag = 0x80000000,
1251 PHYAR_Write = 0x80000000,
1252 PHYAR_Read = 0x00000000,
1253 PHYAR_Reg_Mask = 0x1f,
1255 PHYAR_Data_Mask = 0xffff,
1258 EPHYAR_Flag = 0x80000000,
1259 EPHYAR_Write = 0x80000000,
1260 EPHYAR_Read = 0x00000000,
1261 EPHYAR_Reg_Mask = 0x3f,
1263 EPHYAR_Data_Mask = 0xffff,
1266 CSIAR_Flag = 0x80000000,
1267 CSIAR_Write = 0x80000000,
1268 CSIAR_Read = 0x00000000,
1269 CSIAR_ByteEn = 0x0f,
1271 CSIAR_Addr_Mask = 0x0fff,
1274 ERIAR_Flag = 0x80000000,
1275 ERIAR_Write = 0x80000000,
1276 ERIAR_Read = 0x00000000,
1278 ERIAR_ExGMAC = 0,
1283 ERIAR_ByteEn = 0x0f,
1287 OCPDR_Write = 0x80000000,
1288 OCPDR_Read = 0x00000000,
1289 OCPDR_Reg_Mask = 0xFF,
1290 OCPDR_Data_Mask = 0xFFFF,
1292 OCPAR_Flag = 0x80000000,
1293 OCPAR_GPHY_Write = 0x8000F060,
1294 OCPAR_GPHY_Read = 0x0000F060,
1295 OCPR_Write = 0x80000000,
1296 OCPR_Read = 0x00000000,
1298 OCPR_Flag = 0x80000000,
1299 OCP_STD_PHY_BASE_PAGE = 0x0A40,
1307 EFUSE_WRITE = 0x80000000,
1308 EFUSE_WRITE_OK = 0x00000000,
1309 EFUSE_READ = 0x00000000,
1310 EFUSE_READ_OK = 0x80000000,
1311 EFUSE_WRITE_V3 = 0x40000000,
1312 EFUSE_WRITE_OK_V3 = 0x00000000,
1313 EFUSE_READ_V3 = 0x80000000,
1314 EFUSE_READ_OK_V3 = 0x00000000,
1315 EFUSE_Reg_Mask = 0x03FF,
1318 EFUSE_READ_FAIL = 0xFF,
1319 EFUSE_Data_Mask = 0x000000FF,
1322 GPIO_en = (1 << 0),
1333 /*------ offset 0 of tx descriptor ------*/
1339 MSSMask = 0x7FFU, /* MSS value 11 bits */
1354 /*------ offset 0 of rx descriptor ------*/
1368 /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only begin @@@@@@*/
1371 /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only end @@@@@@*/
1380 // RTL_FEATURE_WOL = (1 << 0),
1385 WOL_DISABLED = 0,
1390 BIT_0 = (1 << 0),
1425 EFUSE_NOT_SUPPORT = 0,
1430 #define RsvdMask 0x3fffc000
1531 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
1709 EEPROM_TYPE_NONE=0,
1716 CFG_METHOD_1=0,
1750 CFG_METHOD_DEFAULT = 0xFF
1761 #define GTTCPHO_MAX 0x7fU
1762 #define GTPKTSIZE_MAX 0x3ffffU
1764 #define TCPHO_MAX 0x3ffU
1765 #define LSOPKTSIZE_MAX 0xffffU
1766 #define MSS_MAX 0x07ffu /* MSS value */
1768 #define OOB_CMD_RESET 0x00
1769 #define OOB_CMD_DRIVER_START 0x05
1770 #define OOB_CMD_DRIVER_STOP 0x06
1771 #define OOB_CMD_SET_IPMAC 0x41
1773 #define WAKEUP_MAGIC_PACKET_NOT_SUPPORT (0)
1778 #define NIC_RAMCODE_VERSION_CFG_METHOD_14 (0x0057)
1779 #define NIC_RAMCODE_VERSION_CFG_METHOD_16 (0x0055)
1780 #define NIC_RAMCODE_VERSION_CFG_METHOD_18 (0x0052)
1781 #define NIC_RAMCODE_VERSION_CFG_METHOD_20 (0x0044)
1782 #define NIC_RAMCODE_VERSION_CFG_METHOD_21 (0x0042)
1783 #define NIC_RAMCODE_VERSION_CFG_METHOD_24 (0x0001)
1784 #define NIC_RAMCODE_VERSION_CFG_METHOD_23 (0x0015)
1785 #define NIC_RAMCODE_VERSION_CFG_METHOD_26 (0x0012)
1786 #define NIC_RAMCODE_VERSION_CFG_METHOD_28 (0x0019)
1787 #define NIC_RAMCODE_VERSION_CFG_METHOD_29 (0x0055)
1788 #define NIC_RAMCODE_VERSION_CFG_METHOD_31 (0x0003)
1832 #define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0 )
1833 #define HW_SUPP_SERDES_PHY(_M) ((_M)->HwSuppSerDesPhyVer > 0)
1834 #define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) (((_M)->HwHasWrRamCodeToMicroP == TRUE) ? 1 : 0)
1835 #define HW_SUPPORT_UPS_MODE(_M) ((_M)->HwSuppUpsVer > 0)
1839 #define netdev_mc_empty(dev) (netdev_mc_count(dev) == 0)