3312 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3347 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_force_linkspeed()
3349 			txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_force_linkspeed()
3351 		txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_force_linkspeed()
3353 	writel(txreg, base + NvRegTxDeferral);  in nv_force_linkspeed()
3356 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_force_linkspeed()
3360 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_force_linkspeed()
3362 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_force_linkspeed()
3364 	writel(txreg, base + NvRegTxWatermark);  in nv_force_linkspeed()
3396 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3528 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_update_linkspeed()
3532 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;  in nv_update_linkspeed()
3534 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;  in nv_update_linkspeed()
3536 				txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_update_linkspeed()
3541 			txreg = NVREG_TX_DEFERRAL_MII_STRETCH;  in nv_update_linkspeed()
3543 			txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_update_linkspeed()
3545 	writel(txreg, base + NvRegTxDeferral);  in nv_update_linkspeed()
3548 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_update_linkspeed()
3551 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_update_linkspeed()
3553 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_update_linkspeed()
3555 	writel(txreg, base + NvRegTxWatermark);  in nv_update_linkspeed()
5715 	u32 powerstate, txreg;  in nv_probe()  local
5893 	txreg = readl(base + NvRegTransmitPoll);  in nv_probe()
5902 	} else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {  in nv_probe()
5926 		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);  in nv_probe()