3312 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3322 		phyreg = readl(base + NvRegSlotTime);  in nv_force_linkspeed()
3323 		phyreg &= ~(0x3FF00);  in nv_force_linkspeed()
3325 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3327 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3329 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_force_linkspeed()
3330 		writel(phyreg, base + NvRegSlotTime);  in nv_force_linkspeed()
3333 	phyreg = readl(base + NvRegPhyInterface);  in nv_force_linkspeed()
3334 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_force_linkspeed()
3336 		phyreg |= PHY_HALF;  in nv_force_linkspeed()
3338 		phyreg |= PHY_100;  in nv_force_linkspeed()
3341 		phyreg |= PHY_1000;  in nv_force_linkspeed()
3342 	writel(phyreg, base + NvRegPhyInterface);  in nv_force_linkspeed()
3344 	if (phyreg & PHY_RGMII) {  in nv_force_linkspeed()
3396 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3505 		phyreg = readl(base + NvRegSlotTime);  in nv_update_linkspeed()
3506 		phyreg &= ~(0x3FF00);  in nv_update_linkspeed()
3509 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_update_linkspeed()
3511 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_update_linkspeed()
3512 		writel(phyreg, base + NvRegSlotTime);  in nv_update_linkspeed()
3515 	phyreg = readl(base + NvRegPhyInterface);  in nv_update_linkspeed()
3516 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_update_linkspeed()
3518 		phyreg |= PHY_HALF;  in nv_update_linkspeed()
3520 		phyreg |= PHY_100;  in nv_update_linkspeed()
3522 		phyreg |= PHY_1000;  in nv_update_linkspeed()
3523 	writel(phyreg, base + NvRegPhyInterface);  in nv_update_linkspeed()
3526 	if (phyreg & PHY_RGMII) {  in nv_update_linkspeed()