Lines Matching refs:val64
120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ argument
1010 register u64 val64 = 0; in s2io_verify_pci_mode() local
1013 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1014 mode = (u8)GET_PCI_MODE(val64); in s2io_verify_pci_mode()
1016 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_verify_pci_mode()
1044 register u64 val64 = 0; in s2io_print_pci_mode() local
1049 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1050 mode = (u8)GET_PCI_MODE(val64); in s2io_print_pci_mode()
1052 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_print_pci_mode()
1094 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode); in s2io_print_pci_mode()
1112 register u64 val64 = 0; in init_tti() local
1124 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); in init_tti()
1126 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); in init_tti()
1128 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | in init_tti()
1134 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; in init_tti()
1135 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1138 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | in init_tti()
1149 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) | in init_tti()
1154 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | in init_tti()
1160 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1162 val64 = TTI_CMD_MEM_WE | in init_tti()
1165 writeq(val64, &bar0->tti_command_mem); in init_tti()
1189 register u64 val64 = 0; in init_nic() local
1209 val64 = 0xA500000000ULL; in init_nic()
1210 writeq(val64, &bar0->sw_reset); in init_nic()
1212 val64 = readq(&bar0->sw_reset); in init_nic()
1216 val64 = 0; in init_nic()
1217 writeq(val64, &bar0->sw_reset); in init_nic()
1219 val64 = readq(&bar0->sw_reset); in init_nic()
1226 val64 = readq(&bar0->adapter_status); in init_nic()
1227 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING)) in init_nic()
1237 val64 = readq(&bar0->mac_cfg); in init_nic()
1238 val64 |= MAC_RMAC_BCAST_ENABLE; in init_nic()
1240 writel((u32)val64, add); in init_nic()
1242 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1245 val64 = readq(&bar0->mac_int_mask); in init_nic()
1246 val64 = readq(&bar0->mc_int_mask); in init_nic()
1247 val64 = readq(&bar0->xgxs_int_mask); in init_nic()
1250 val64 = dev->mtu; in init_nic()
1251 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1265 val64 = readq(&bar0->dtx_control); in init_nic()
1271 val64 = 0; in init_nic()
1272 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1273 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1274 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1275 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1280 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) | in init_nic()
1290 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1291 val64 = 0; in init_nic()
1295 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1296 val64 = 0; in init_nic()
1300 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1301 val64 = 0; in init_nic()
1305 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1306 val64 = 0; in init_nic()
1322 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1324 &bar0->tx_fifo_partition_0, (unsigned long long)val64); in init_nic()
1330 val64 = readq(&bar0->tx_pa_cfg); in init_nic()
1331 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | in init_nic()
1335 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1338 val64 = 0; in init_nic()
1342 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3); in init_nic()
1344 writeq(val64, &bar0->rx_queue_priority); in init_nic()
1350 val64 = 0; in init_nic()
1361 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); in init_nic()
1365 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); in init_nic()
1369 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); in init_nic()
1373 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); in init_nic()
1377 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); in init_nic()
1381 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); in init_nic()
1385 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); in init_nic()
1389 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); in init_nic()
1393 writeq(val64, &bar0->rx_queue_cfg); in init_nic()
1401 val64 = 0x0; in init_nic()
1402 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1403 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1404 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1405 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1406 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1409 val64 = 0x0001000100010001ULL; in init_nic()
1410 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1411 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1412 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1413 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1414 val64 = 0x0001000100000000ULL; in init_nic()
1415 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1418 val64 = 0x0001020001020001ULL; in init_nic()
1419 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1420 val64 = 0x0200010200010200ULL; in init_nic()
1421 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1422 val64 = 0x0102000102000102ULL; in init_nic()
1423 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1424 val64 = 0x0001020001020001ULL; in init_nic()
1425 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1426 val64 = 0x0200010200000000ULL; in init_nic()
1427 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1430 val64 = 0x0001020300010203ULL; in init_nic()
1431 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1432 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1433 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1434 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1435 val64 = 0x0001020300000000ULL; in init_nic()
1436 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1439 val64 = 0x0001020304000102ULL; in init_nic()
1440 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1441 val64 = 0x0304000102030400ULL; in init_nic()
1442 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1443 val64 = 0x0102030400010203ULL; in init_nic()
1444 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1445 val64 = 0x0400010203040001ULL; in init_nic()
1446 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1447 val64 = 0x0203040000000000ULL; in init_nic()
1448 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1451 val64 = 0x0001020304050001ULL; in init_nic()
1452 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1453 val64 = 0x0203040500010203ULL; in init_nic()
1454 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1455 val64 = 0x0405000102030405ULL; in init_nic()
1456 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1457 val64 = 0x0001020304050001ULL; in init_nic()
1458 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1459 val64 = 0x0203040500000000ULL; in init_nic()
1460 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1463 val64 = 0x0001020304050600ULL; in init_nic()
1464 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1465 val64 = 0x0102030405060001ULL; in init_nic()
1466 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1467 val64 = 0x0203040506000102ULL; in init_nic()
1468 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1469 val64 = 0x0304050600010203ULL; in init_nic()
1470 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1471 val64 = 0x0405060000000000ULL; in init_nic()
1472 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1475 val64 = 0x0001020304050607ULL; in init_nic()
1476 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1477 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1478 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1479 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1480 val64 = 0x0001020300000000ULL; in init_nic()
1481 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1486 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1487 val64 |= (TX_FIFO_PARTITION_EN); in init_nic()
1488 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1496 val64 = 0x0; in init_nic()
1497 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1498 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1499 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1500 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1501 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1503 val64 = 0x8080808080808080ULL; in init_nic()
1504 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1507 val64 = 0x0001000100010001ULL; in init_nic()
1508 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1509 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1510 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1511 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1512 val64 = 0x0001000100000000ULL; in init_nic()
1513 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1515 val64 = 0x8080808040404040ULL; in init_nic()
1516 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1519 val64 = 0x0001020001020001ULL; in init_nic()
1520 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1521 val64 = 0x0200010200010200ULL; in init_nic()
1522 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1523 val64 = 0x0102000102000102ULL; in init_nic()
1524 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1525 val64 = 0x0001020001020001ULL; in init_nic()
1526 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1527 val64 = 0x0200010200000000ULL; in init_nic()
1528 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1530 val64 = 0x8080804040402020ULL; in init_nic()
1531 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1534 val64 = 0x0001020300010203ULL; in init_nic()
1535 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1536 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1537 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1538 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1539 val64 = 0x0001020300000000ULL; in init_nic()
1540 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1542 val64 = 0x8080404020201010ULL; in init_nic()
1543 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1546 val64 = 0x0001020304000102ULL; in init_nic()
1547 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1548 val64 = 0x0304000102030400ULL; in init_nic()
1549 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1550 val64 = 0x0102030400010203ULL; in init_nic()
1551 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1552 val64 = 0x0400010203040001ULL; in init_nic()
1553 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1554 val64 = 0x0203040000000000ULL; in init_nic()
1555 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1557 val64 = 0x8080404020201008ULL; in init_nic()
1558 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1561 val64 = 0x0001020304050001ULL; in init_nic()
1562 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1563 val64 = 0x0203040500010203ULL; in init_nic()
1564 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1565 val64 = 0x0405000102030405ULL; in init_nic()
1566 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1567 val64 = 0x0001020304050001ULL; in init_nic()
1568 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1569 val64 = 0x0203040500000000ULL; in init_nic()
1570 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1572 val64 = 0x8080404020100804ULL; in init_nic()
1573 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1576 val64 = 0x0001020304050600ULL; in init_nic()
1577 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1578 val64 = 0x0102030405060001ULL; in init_nic()
1579 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1580 val64 = 0x0203040506000102ULL; in init_nic()
1581 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1582 val64 = 0x0304050600010203ULL; in init_nic()
1583 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1584 val64 = 0x0405060000000000ULL; in init_nic()
1585 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1587 val64 = 0x8080402010080402ULL; in init_nic()
1588 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1591 val64 = 0x0001020304050607ULL; in init_nic()
1592 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1593 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1594 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1595 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1596 val64 = 0x0001020300000000ULL; in init_nic()
1597 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1599 val64 = 0x8040201008040201ULL; in init_nic()
1600 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1605 val64 = 0; in init_nic()
1607 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1610 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); in init_nic()
1612 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1644 val64 = STAT_BC(0x320); in init_nic()
1645 writeq(val64, &bar0->stat_byte_cnt); in init_nic()
1652 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) | in init_nic()
1654 writeq(val64, &bar0->mac_link_util); in init_nic()
1672 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); in init_nic()
1674 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); in init_nic()
1675 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | in init_nic()
1680 writeq(val64, &bar0->rti_data1_mem); in init_nic()
1682 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | in init_nic()
1685 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | in init_nic()
1688 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | in init_nic()
1690 writeq(val64, &bar0->rti_data2_mem); in init_nic()
1693 val64 = RTI_CMD_MEM_WE | in init_nic()
1696 writeq(val64, &bar0->rti_command_mem); in init_nic()
1707 val64 = readq(&bar0->rti_command_mem); in init_nic()
1708 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) in init_nic()
1730 val64 = readq(&bar0->mac_cfg); in init_nic()
1731 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); in init_nic()
1733 writel((u32) (val64), add); in init_nic()
1735 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1736 val64 = readq(&bar0->mac_cfg); in init_nic()
1740 val64 = readq(&bar0->mac_cfg); in init_nic()
1741 val64 |= MAC_CFG_RMAC_STRIP_FCS; in init_nic()
1743 writeq(val64, &bar0->mac_cfg); in init_nic()
1746 writel((u32) (val64), add); in init_nic()
1748 writel((u32) (val64 >> 32), (add + 4)); in init_nic()
1755 val64 = readq(&bar0->rmac_pause_cfg); in init_nic()
1756 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff)); in init_nic()
1757 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); in init_nic()
1758 writeq(val64, &bar0->rmac_pause_cfg); in init_nic()
1766 val64 = 0; in init_nic()
1768 val64 |= (((u64)0xFF00 | in init_nic()
1772 writeq(val64, &bar0->mc_pause_thresh_q0q3); in init_nic()
1774 val64 = 0; in init_nic()
1776 val64 |= (((u64)0xFF00 | in init_nic()
1780 writeq(val64, &bar0->mc_pause_thresh_q4q7); in init_nic()
1786 val64 = readq(&bar0->pic_control); in init_nic()
1787 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); in init_nic()
1788 writeq(val64, &bar0->pic_control); in init_nic()
1801 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN | in init_nic()
1803 writeq(val64, &bar0->misc_control); in init_nic()
1804 val64 = readq(&bar0->pic_control2); in init_nic()
1805 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15)); in init_nic()
1806 writeq(val64, &bar0->pic_control2); in init_nic()
1809 val64 = TMAC_AVG_IPG(0x17); in init_nic()
1810 writeq(val64, &bar0->tmac_avg_ipg); in init_nic()
2077 u64 val64 = readq(&bar0->adapter_status); in verify_pcc_quiescent() local
2083 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE)) in verify_pcc_quiescent()
2086 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) in verify_pcc_quiescent()
2091 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == in verify_pcc_quiescent()
2095 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == in verify_pcc_quiescent()
2119 u64 val64 = readq(&bar0->adapter_status); in verify_xena_quiescence() local
2122 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) { in verify_xena_quiescence()
2126 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) { in verify_xena_quiescence()
2130 if (!(val64 & ADAPTER_STATUS_PFC_READY)) { in verify_xena_quiescence()
2134 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) { in verify_xena_quiescence()
2138 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) { in verify_xena_quiescence()
2142 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) { in verify_xena_quiescence()
2146 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) { in verify_xena_quiescence()
2150 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) { in verify_xena_quiescence()
2160 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) && in verify_xena_quiescence()
2166 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == in verify_xena_quiescence()
2211 register u64 val64 = 0; in start_nic() local
2223 val64 = readq(&bar0->prc_ctrl_n[i]); in start_nic()
2225 val64 |= PRC_CTRL_RC_ENABLED; in start_nic()
2227 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; in start_nic()
2229 val64 |= PRC_CTRL_GROUP_READS; in start_nic()
2230 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF); in start_nic()
2231 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000); in start_nic()
2232 writeq(val64, &bar0->prc_ctrl_n[i]); in start_nic()
2237 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2238 val64 |= RX_PA_CFG_IGNORE_L2_ERR; in start_nic()
2239 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2243 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2244 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; in start_nic()
2245 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2254 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2255 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; in start_nic()
2256 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in start_nic()
2257 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2262 val64 = readq(&bar0->adapter_control); in start_nic()
2263 val64 &= ~ADAPTER_ECC_EN; in start_nic()
2264 writeq(val64, &bar0->adapter_control); in start_nic()
2270 val64 = readq(&bar0->adapter_status); in start_nic()
2274 dev->name, (unsigned long long)val64); in start_nic()
2287 val64 = readq(&bar0->adapter_control); in start_nic()
2288 val64 |= ADAPTER_EOI_TX_ON; in start_nic()
2289 writeq(val64, &bar0->adapter_control); in start_nic()
2302 val64 = readq(&bar0->gpio_control); in start_nic()
2303 val64 |= 0x0000800000000000ULL; in start_nic()
2304 writeq(val64, &bar0->gpio_control); in start_nic()
2305 val64 = 0x0411040400000000ULL; in start_nic()
2306 writeq(val64, (void __iomem *)bar0 + 0x2700); in start_nic()
2413 register u64 val64 = 0; in stop_nic() local
2423 val64 = readq(&bar0->adapter_control); in stop_nic()
2424 val64 &= ~(ADAPTER_CNTL_EN); in stop_nic()
2425 writeq(val64, &bar0->adapter_control); in stop_nic()
2833 u64 val64 = 0xFFFFFFFFFFFFFFFFULL; in s2io_netpoll() local
2843 writeq(val64, &bar0->rx_traffic_int); in s2io_netpoll()
2844 writeq(val64, &bar0->tx_traffic_int); in s2io_netpoll()
3086 u64 val64; in s2io_mdio_write() local
3091 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3094 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3095 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3096 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3100 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3105 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3106 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3107 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3110 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_write()
3114 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3115 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write()
3116 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3131 u64 val64 = 0x0; in s2io_mdio_read() local
3137 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr) in s2io_mdio_read()
3140 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3141 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read()
3142 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3146 val64 = MDIO_MMD_INDX_ADDR(addr) | in s2io_mdio_read()
3150 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3151 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read()
3152 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3178 u64 val64; in s2io_chk_xpak_counter() local
3185 val64 = *regs_stat & mask; in s2io_chk_xpak_counter()
3186 val64 = val64 >> (index * 0x2); in s2io_chk_xpak_counter()
3187 val64 = val64 + 1; in s2io_chk_xpak_counter()
3188 if (val64 == 3) { in s2io_chk_xpak_counter()
3212 val64 = 0x0; in s2io_chk_xpak_counter()
3214 val64 = val64 << (index * 0x2); in s2io_chk_xpak_counter()
3215 *regs_stat = (*regs_stat & (~mask)) | (val64); in s2io_chk_xpak_counter()
3234 u64 val64 = 0x0; in s2io_updt_xpak_counter() local
3243 val64 = 0x0; in s2io_updt_xpak_counter()
3244 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3245 if ((val64 == 0xFFFF) || (val64 == 0x0000)) { in s2io_updt_xpak_counter()
3248 (unsigned long long)val64); in s2io_updt_xpak_counter()
3253 if (val64 != MDIO_CTRL1_SPEED10G) { in s2io_updt_xpak_counter()
3256 (unsigned long long)val64, MDIO_CTRL1_SPEED10G); in s2io_updt_xpak_counter()
3263 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3267 val64 = 0x0; in s2io_updt_xpak_counter()
3268 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3270 flag = CHECKBIT(val64, 0x7); in s2io_updt_xpak_counter()
3276 if (CHECKBIT(val64, 0x6)) in s2io_updt_xpak_counter()
3279 flag = CHECKBIT(val64, 0x3); in s2io_updt_xpak_counter()
3285 if (CHECKBIT(val64, 0x2)) in s2io_updt_xpak_counter()
3288 flag = CHECKBIT(val64, 0x1); in s2io_updt_xpak_counter()
3294 if (CHECKBIT(val64, 0x0)) in s2io_updt_xpak_counter()
3299 val64 = 0x0; in s2io_updt_xpak_counter()
3300 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); in s2io_updt_xpak_counter()
3302 if (CHECKBIT(val64, 0x7)) in s2io_updt_xpak_counter()
3305 if (CHECKBIT(val64, 0x6)) in s2io_updt_xpak_counter()
3308 if (CHECKBIT(val64, 0x3)) in s2io_updt_xpak_counter()
3311 if (CHECKBIT(val64, 0x2)) in s2io_updt_xpak_counter()
3314 if (CHECKBIT(val64, 0x1)) in s2io_updt_xpak_counter()
3317 if (CHECKBIT(val64, 0x0)) in s2io_updt_xpak_counter()
3337 u64 val64; in wait_for_cmd_complete() local
3343 val64 = readq(addr); in wait_for_cmd_complete()
3345 if (!(val64 & busy_bit)) { in wait_for_cmd_complete()
3350 if (val64 & busy_bit) { in wait_for_cmd_complete()
3399 u64 val64; in s2io_reset() local
3414 val64 = SW_RESET_ALL; in s2io_reset()
3415 writeq(val64, &bar0->sw_reset); in s2io_reset()
3490 val64 = readq(&bar0->gpio_control); in s2io_reset()
3491 val64 |= 0x0000800000000000ULL; in s2io_reset()
3492 writeq(val64, &bar0->gpio_control); in s2io_reset()
3493 val64 = 0x0411040400000000ULL; in s2io_reset()
3494 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_reset()
3502 val64 = readq(&bar0->pcc_err_reg); in s2io_reset()
3503 writeq(val64, &bar0->pcc_err_reg); in s2io_reset()
3523 u64 val64, valt, valr; in s2io_set_swapper() local
3530 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3531 if (val64 != 0x0123456789ABCDEFULL) { in s2io_set_swapper()
3542 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3543 if (val64 == 0x0123456789ABCDEFULL) in s2io_set_swapper()
3550 dev->name, (unsigned long long)val64); in s2io_set_swapper()
3560 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3562 if (val64 != valt) { in s2io_set_swapper()
3574 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3575 if (val64 == valt) in s2io_set_swapper()
3580 unsigned long long x = val64; in s2io_set_swapper()
3586 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3587 val64 &= 0xFFFF000000000000ULL; in s2io_set_swapper()
3594 val64 |= (SWAPPER_CTRL_TXP_FE | in s2io_set_swapper()
3606 val64 |= SWAPPER_CTRL_XMSI_SE; in s2io_set_swapper()
3607 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3614 val64 |= (SWAPPER_CTRL_TXP_FE | in s2io_set_swapper()
3630 val64 |= SWAPPER_CTRL_XMSI_SE; in s2io_set_swapper()
3631 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3633 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3639 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3640 if (val64 != 0x0123456789ABCDEFULL) { in s2io_set_swapper()
3644 dev->name, (unsigned long long)val64); in s2io_set_swapper()
3654 u64 val64; in wait_for_msix_trans() local
3658 val64 = readq(&bar0->xmsi_access); in wait_for_msix_trans()
3659 if (!(val64 & s2BIT(15))) in wait_for_msix_trans()
3675 u64 val64; in restore_xmsi_data() local
3685 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6)); in restore_xmsi_data()
3686 writeq(val64, &bar0->xmsi_access); in restore_xmsi_data()
3696 u64 val64, addr, data; in store_xmsi_data() local
3705 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6)); in store_xmsi_data()
3706 writeq(val64, &bar0->xmsi_access); in store_xmsi_data()
3822 u64 val64, saved64; in s2io_test_msi() local
3835 saved64 = val64 = readq(&bar0->scheduled_int_ctrl); in s2io_test_msi()
3836 val64 |= SCHED_INT_CTRL_ONE_SHOT; in s2io_test_msi()
3837 val64 |= SCHED_INT_CTRL_TIMER_EN; in s2io_test_msi()
3838 val64 |= SCHED_INT_CTRL_INT2MSI(1); in s2io_test_msi()
3839 writeq(val64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
4007 register u64 val64; in s2io_xmit() local
4150 val64 = fifo->list_info[put_off].list_phy_addr; in s2io_xmit()
4151 writeq(val64, &tx_fifo->TxDL_Pointer); in s2io_xmit()
4153 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | in s2io_xmit()
4156 val64 |= TX_FIFO_SPECIAL_FUNC; in s2io_xmit()
4158 writeq(val64, &tx_fifo->List_Control); in s2io_xmit()
4267 u64 val64; in s2io_txpic_intr_handle() local
4269 val64 = readq(&bar0->pic_int_status); in s2io_txpic_intr_handle()
4270 if (val64 & PIC_INT_GPIO) { in s2io_txpic_intr_handle()
4271 val64 = readq(&bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4272 if ((val64 & GPIO_INT_REG_LINK_DOWN) && in s2io_txpic_intr_handle()
4273 (val64 & GPIO_INT_REG_LINK_UP)) { in s2io_txpic_intr_handle()
4278 val64 |= GPIO_INT_REG_LINK_DOWN; in s2io_txpic_intr_handle()
4279 val64 |= GPIO_INT_REG_LINK_UP; in s2io_txpic_intr_handle()
4280 writeq(val64, &bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4281 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4282 val64 &= ~(GPIO_INT_MASK_LINK_UP | in s2io_txpic_intr_handle()
4284 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4285 } else if (val64 & GPIO_INT_REG_LINK_UP) { in s2io_txpic_intr_handle()
4286 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4288 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4289 val64 |= ADAPTER_CNTL_EN; in s2io_txpic_intr_handle()
4290 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4291 val64 |= ADAPTER_LED_ON; in s2io_txpic_intr_handle()
4292 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4301 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4302 val64 &= ~GPIO_INT_MASK_LINK_DOWN; in s2io_txpic_intr_handle()
4303 val64 |= GPIO_INT_MASK_LINK_UP; in s2io_txpic_intr_handle()
4304 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4306 } else if (val64 & GPIO_INT_REG_LINK_DOWN) { in s2io_txpic_intr_handle()
4307 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4310 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4311 val64 &= ~GPIO_INT_MASK_LINK_UP; in s2io_txpic_intr_handle()
4312 val64 |= GPIO_INT_MASK_LINK_DOWN; in s2io_txpic_intr_handle()
4313 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4316 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4317 val64 = val64 & (~ADAPTER_LED_ON); in s2io_txpic_intr_handle()
4318 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4321 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4337 u64 val64; in do_s2io_chk_alarm_bit() local
4338 val64 = readq(addr); in do_s2io_chk_alarm_bit()
4339 if (val64 & value) { in do_s2io_chk_alarm_bit()
4340 writeq(val64, addr); in do_s2io_chk_alarm_bit()
4361 u64 temp64 = 0, val64 = 0; in s2io_handle_errors() local
4388 val64 = readq(&bar0->mac_rmac_err_reg); in s2io_handle_errors()
4389 writeq(val64, &bar0->mac_rmac_err_reg); in s2io_handle_errors()
4390 if (val64 & RMAC_LINK_STATE_CHANGE_INT) in s2io_handle_errors()
4406 val64 = readq(&bar0->ring_bump_counter1); in s2io_handle_errors()
4408 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); in s2io_handle_errors()
4413 val64 = readq(&bar0->ring_bump_counter2); in s2io_handle_errors()
4415 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); in s2io_handle_errors()
4421 val64 = readq(&bar0->txdma_int_status); in s2io_handle_errors()
4423 if (val64 & TXDMA_PFC_INT) { in s2io_handle_errors()
4436 if (val64 & TXDMA_TDA_INT) { in s2io_handle_errors()
4448 if (val64 & TXDMA_PCC_INT) { in s2io_handle_errors()
4463 if (val64 & TXDMA_TTI_INT) { in s2io_handle_errors()
4474 if (val64 & TXDMA_LSO_INT) { in s2io_handle_errors()
4486 if (val64 & TXDMA_TPA_INT) { in s2io_handle_errors()
4497 if (val64 & TXDMA_SM_INT) { in s2io_handle_errors()
4504 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4505 if (val64 & MAC_INT_STATUS_TMAC_INT) { in s2io_handle_errors()
4517 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4518 if (val64 & XGXS_INT_STATUS_TXGXS) { in s2io_handle_errors()
4528 val64 = readq(&bar0->rxdma_int_status); in s2io_handle_errors()
4529 if (val64 & RXDMA_INT_RC_INT_M) { in s2io_handle_errors()
4554 if (val64 & RXDMA_INT_RPA_INT_M) { in s2io_handle_errors()
4564 if (val64 & RXDMA_INT_RDA_INT_M) { in s2io_handle_errors()
4581 if (val64 & RXDMA_INT_RTI_INT_M) { in s2io_handle_errors()
4591 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4592 if (val64 & MAC_INT_STATUS_RMAC_INT) { in s2io_handle_errors()
4604 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4605 if (val64 & XGXS_INT_STATUS_RXGXS) { in s2io_handle_errors()
4612 val64 = readq(&bar0->mc_int_status); in s2io_handle_errors()
4613 if (val64 & MC_INT_STATUS_MC_INT) { in s2io_handle_errors()
4620 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) { in s2io_handle_errors()
4621 writeq(val64, &bar0->mc_err_reg); in s2io_handle_errors()
4622 if (val64 & MC_ERR_REG_ECC_ALL_DBL) { in s2io_handle_errors()
4628 if (val64 & in s2io_handle_errors()
4760 u64 val64; in s2io_updt_stats() local
4765 val64 = SET_UPDT_CLICKS(10) | in s2io_updt_stats()
4767 writeq(val64, &bar0->stat_cfg); in s2io_updt_stats()
4770 val64 = readq(&bar0->stat_cfg); in s2io_updt_stats()
4771 if (!(val64 & s2BIT(0))) in s2io_updt_stats()
4887 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = in s2io_set_multicast() local
4899 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
4902 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4916 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
4919 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4932 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4933 val64 |= MAC_CFG_RMAC_PROM_ENABLE; in s2io_set_multicast()
4936 writel((u32)val64, add); in s2io_set_multicast()
4938 writel((u32) (val64 >> 32), (add + 4)); in s2io_set_multicast()
4941 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4942 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; in s2io_set_multicast()
4943 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4947 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4954 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4955 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; in s2io_set_multicast()
4958 writel((u32)val64, add); in s2io_set_multicast()
4960 writel((u32) (val64 >> 32), (add + 4)); in s2io_set_multicast()
4963 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4964 val64 |= RX_PA_CFG_STRIP_VLAN_TAG; in s2io_set_multicast()
4965 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4969 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4994 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
4998 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5024 val64 = RMAC_ADDR_CMD_MEM_WE | in s2io_set_multicast()
5028 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5117 u64 val64; in do_s2io_add_mac() local
5123 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in do_s2io_add_mac()
5125 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_add_mac()
5163 u64 tmp64, val64; in do_s2io_read_unicast_mc() local
5167 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in do_s2io_read_unicast_mc()
5169 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_read_unicast_mc()
5382 u64 val64; in s2io_set_led() local
5386 val64 = readq(&bar0->gpio_control); in s2io_set_led()
5388 val64 |= GPIO_CTRL_GPIO_0; in s2io_set_led()
5390 val64 &= ~GPIO_CTRL_GPIO_0; in s2io_set_led()
5392 writeq(val64, &bar0->gpio_control); in s2io_set_led()
5394 val64 = readq(&bar0->adapter_control); in s2io_set_led()
5396 val64 |= ADAPTER_LED_ON; in s2io_set_led()
5398 val64 &= ~ADAPTER_LED_ON; in s2io_set_led()
5400 writeq(val64, &bar0->adapter_control); in s2io_set_led()
5425 u64 val64 = readq(&bar0->adapter_control); in s2io_ethtool_set_led() local
5426 if (!(val64 & ADAPTER_CNTL_EN)) { in s2io_ethtool_set_led()
5492 u64 val64; in s2io_ethtool_getpause_data() local
5496 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_getpause_data()
5497 if (val64 & RMAC_PAUSE_GEN_ENABLE) in s2io_ethtool_getpause_data()
5499 if (val64 & RMAC_PAUSE_RX_ENABLE) in s2io_ethtool_getpause_data()
5518 u64 val64; in s2io_ethtool_setpause_data() local
5522 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5524 val64 |= RMAC_PAUSE_GEN_ENABLE; in s2io_ethtool_setpause_data()
5526 val64 &= ~RMAC_PAUSE_GEN_ENABLE; in s2io_ethtool_setpause_data()
5528 val64 |= RMAC_PAUSE_RX_ENABLE; in s2io_ethtool_setpause_data()
5530 val64 &= ~RMAC_PAUSE_RX_ENABLE; in s2io_ethtool_setpause_data()
5531 writeq(val64, &bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5555 u64 val64; in read_eeprom() local
5559 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | in read_eeprom()
5564 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in read_eeprom()
5567 val64 = readq(&bar0->i2c_control); in read_eeprom()
5568 if (I2C_CONTROL_CNTL_END(val64)) { in read_eeprom()
5569 *data = I2C_CONTROL_GET_DATA(val64); in read_eeprom()
5579 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | in read_eeprom()
5582 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5583 val64 |= SPI_CONTROL_REQ; in read_eeprom()
5584 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5586 val64 = readq(&bar0->spi_control); in read_eeprom()
5587 if (val64 & SPI_CONTROL_NACK) { in read_eeprom()
5590 } else if (val64 & SPI_CONTROL_DONE) { in read_eeprom()
5621 u64 val64; in write_eeprom() local
5625 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | in write_eeprom()
5630 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in write_eeprom()
5633 val64 = readq(&bar0->i2c_control); in write_eeprom()
5634 if (I2C_CONTROL_CNTL_END(val64)) { in write_eeprom()
5635 if (!(val64 & I2C_CONTROL_NACK)) in write_eeprom()
5648 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | in write_eeprom()
5651 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5652 val64 |= SPI_CONTROL_REQ; in write_eeprom()
5653 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5655 val64 = readq(&bar0->spi_control); in write_eeprom()
5656 if (val64 & SPI_CONTROL_NACK) { in write_eeprom()
5659 } else if (val64 & SPI_CONTROL_DONE) { in write_eeprom()
5842 u64 val64 = 0, exp_val; in s2io_register_test() local
5845 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_register_test()
5846 if (val64 != 0x123456789abcdefULL) { in s2io_register_test()
5851 val64 = readq(&bar0->rmac_pause_cfg); in s2io_register_test()
5852 if (val64 != 0xc000ffff00000000ULL) { in s2io_register_test()
5857 val64 = readq(&bar0->rx_queue_cfg); in s2io_register_test()
5862 if (val64 != exp_val) { in s2io_register_test()
5867 val64 = readq(&bar0->xgxs_efifo_cfg); in s2io_register_test()
5868 if (val64 != 0x000000001923141EULL) { in s2io_register_test()
5873 val64 = 0x5A5A5A5A5A5A5A5AULL; in s2io_register_test()
5874 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5875 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5876 if (val64 != 0x5A5A5A5A5A5A5A5AULL) { in s2io_register_test()
5881 val64 = 0xA5A5A5A5A5A5A5A5ULL; in s2io_register_test()
5882 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5883 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5884 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { in s2io_register_test()
6047 u64 val64; in s2io_link_test() local
6049 val64 = readq(&bar0->adapter_status); in s2io_link_test()
6050 if (!(LINK_IS_UP(val64))) in s2io_link_test()
6074 u64 val64; in s2io_rldram_test() local
6077 val64 = readq(&bar0->adapter_control); in s2io_rldram_test()
6078 val64 &= ~ADAPTER_ECC_EN; in s2io_rldram_test()
6079 writeq(val64, &bar0->adapter_control); in s2io_rldram_test()
6081 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6082 val64 |= MC_RLDRAM_TEST_MODE; in s2io_rldram_test()
6083 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6085 val64 = readq(&bar0->mc_rldram_mrs); in s2io_rldram_test()
6086 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; in s2io_rldram_test()
6087 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6089 val64 |= MC_RLDRAM_MRS_ENABLE; in s2io_rldram_test()
6090 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6093 val64 = 0x55555555aaaa0000ULL; in s2io_rldram_test()
6095 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6096 writeq(val64, &bar0->mc_rldram_test_d0); in s2io_rldram_test()
6098 val64 = 0xaaaa5a5555550000ULL; in s2io_rldram_test()
6100 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6101 writeq(val64, &bar0->mc_rldram_test_d1); in s2io_rldram_test()
6103 val64 = 0x55aaaaaaaa5a0000ULL; in s2io_rldram_test()
6105 val64 ^= 0xFFFFFFFFFFFF0000ULL; in s2io_rldram_test()
6106 writeq(val64, &bar0->mc_rldram_test_d2); in s2io_rldram_test()
6108 val64 = (u64) (0x0000003ffffe0100ULL); in s2io_rldram_test()
6109 writeq(val64, &bar0->mc_rldram_test_add); in s2io_rldram_test()
6111 val64 = MC_RLDRAM_TEST_MODE | in s2io_rldram_test()
6114 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6117 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6118 if (val64 & MC_RLDRAM_TEST_DONE) in s2io_rldram_test()
6126 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO; in s2io_rldram_test()
6127 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6130 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6131 if (val64 & MC_RLDRAM_TEST_DONE) in s2io_rldram_test()
6139 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6140 if (!(val64 & MC_RLDRAM_TEST_PASS)) in s2io_rldram_test()
6645 u64 val64 = new_mtu; in s2io_change_mtu() local
6647 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in s2io_change_mtu()
6665 register u64 val64; in s2io_set_link() local
6687 val64 = readq(&bar0->adapter_status); in s2io_set_link()
6688 if (LINK_IS_UP(val64)) { in s2io_set_link()
6691 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6692 val64 |= ADAPTER_CNTL_EN; in s2io_set_link()
6693 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6696 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6697 val64 |= GPIO_CTRL_GPIO_0; in s2io_set_link()
6698 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6699 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6701 val64 |= ADAPTER_LED_ON; in s2io_set_link()
6702 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6712 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6713 val64 |= ADAPTER_LED_ON; in s2io_set_link()
6714 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6719 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6720 val64 &= ~GPIO_CTRL_GPIO_0; in s2io_set_link()
6721 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6722 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6725 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6726 val64 = val64 & (~ADAPTER_LED_ON); in s2io_set_link()
6727 writeq(val64, &bar0->adapter_control); in s2io_set_link()
7007 register u64 val64 = 0; in do_s2io_card_down() local
7051 val64 = readq(&bar0->adapter_status); in do_s2io_card_down()
7062 (unsigned long long)val64); in do_s2io_card_down()
7602 register u64 val64 = 0; in rts_ds_steer() local
7607 val64 = RTS_DS_MEM_DATA(ring); in rts_ds_steer()
7608 writeq(val64, &bar0->rts_ds_mem_data); in rts_ds_steer()
7610 val64 = RTS_DS_MEM_CTRL_WE | in rts_ds_steer()
7614 writeq(val64, &bar0->rts_ds_mem_ctrl); in rts_ds_steer()
7660 u64 val64 = 0, tmp64 = 0; in s2io_init_nic() local
7938 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | in s2io_init_nic()
7940 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_init_nic()
8006 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8007 val64 |= 0x0000800000000000ULL; in s2io_init_nic()
8008 writeq(val64, &bar0->gpio_control); in s2io_init_nic()
8009 val64 = 0x0411040400000000ULL; in s2io_init_nic()
8010 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_init_nic()
8011 val64 = readq(&bar0->gpio_control); in s2io_init_nic()