Lines Matching refs:bar0
1009 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_verify_pci_mode() local
1013 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1043 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_print_pci_mode() local
1049 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1111 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_tti() local
1135 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1160 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1165 writeq(val64, &bar0->tti_command_mem); in init_tti()
1167 if (wait_for_cmd_complete(&bar0->tti_command_mem, in init_tti()
1187 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_nic() local
1210 writeq(val64, &bar0->sw_reset); in init_nic()
1212 val64 = readq(&bar0->sw_reset); in init_nic()
1217 writeq(val64, &bar0->sw_reset); in init_nic()
1219 val64 = readq(&bar0->sw_reset); in init_nic()
1226 val64 = readq(&bar0->adapter_status); in init_nic()
1236 add = &bar0->mac_cfg; in init_nic()
1237 val64 = readq(&bar0->mac_cfg); in init_nic()
1239 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1241 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1245 val64 = readq(&bar0->mac_int_mask); in init_nic()
1246 val64 = readq(&bar0->mc_int_mask); in init_nic()
1247 val64 = readq(&bar0->xgxs_int_mask); in init_nic()
1251 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1256 &bar0->dtx_control, UF); in init_nic()
1264 &bar0->dtx_control, UF); in init_nic()
1265 val64 = readq(&bar0->dtx_control); in init_nic()
1272 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1273 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1274 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1275 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1290 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1295 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1300 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1305 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1320 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); in init_nic()
1322 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1324 &bar0->tx_fifo_partition_0, (unsigned long long)val64); in init_nic()
1330 val64 = readq(&bar0->tx_pa_cfg); in init_nic()
1335 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1344 writeq(val64, &bar0->rx_queue_priority); in init_nic()
1393 writeq(val64, &bar0->rx_queue_cfg); in init_nic()
1402 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1403 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1404 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1405 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1406 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1410 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1411 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1412 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1413 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1415 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1419 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1421 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1423 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1425 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1427 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1431 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1432 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1433 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1434 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1436 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1440 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1442 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1444 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1446 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1448 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1452 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1454 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1456 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1458 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1460 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1464 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1466 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1468 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1470 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1472 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1476 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1477 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1478 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1479 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1481 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1486 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1488 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1497 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1498 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1499 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1500 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1501 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1504 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1508 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1509 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1510 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1511 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1513 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1516 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1520 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1522 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1524 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1526 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1528 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1531 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1535 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1536 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1537 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1538 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1540 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1543 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1547 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1549 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1551 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1553 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1555 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1558 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1562 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1564 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1566 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1568 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1570 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1573 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1577 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1579 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1581 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1583 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1585 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1588 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1592 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1593 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1594 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1595 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1597 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1600 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1607 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1612 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1626 &bar0->rts_frm_len_n[i]); in init_nic()
1641 writeq(mac_control->stats_mem_phy, &bar0->stat_addr); in init_nic()
1645 writeq(val64, &bar0->stat_byte_cnt); in init_nic()
1654 writeq(val64, &bar0->mac_link_util); in init_nic()
1680 writeq(val64, &bar0->rti_data1_mem); in init_nic()
1690 writeq(val64, &bar0->rti_data2_mem); in init_nic()
1696 writeq(val64, &bar0->rti_command_mem); in init_nic()
1707 val64 = readq(&bar0->rti_command_mem); in init_nic()
1725 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); in init_nic()
1726 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); in init_nic()
1729 add = &bar0->mac_cfg; in init_nic()
1730 val64 = readq(&bar0->mac_cfg); in init_nic()
1732 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1734 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1736 val64 = readq(&bar0->mac_cfg); in init_nic()
1739 add = &bar0->mac_cfg; in init_nic()
1740 val64 = readq(&bar0->mac_cfg); in init_nic()
1743 writeq(val64, &bar0->mac_cfg); in init_nic()
1745 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1747 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1755 val64 = readq(&bar0->rmac_pause_cfg); in init_nic()
1758 writeq(val64, &bar0->rmac_pause_cfg); in init_nic()
1772 writeq(val64, &bar0->mc_pause_thresh_q0q3); in init_nic()
1780 writeq(val64, &bar0->mc_pause_thresh_q4q7); in init_nic()
1786 val64 = readq(&bar0->pic_control); in init_nic()
1788 writeq(val64, &bar0->pic_control); in init_nic()
1791 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout); in init_nic()
1792 writeq(0x0, &bar0->read_retry_delay); in init_nic()
1793 writeq(0x0, &bar0->write_retry_delay); in init_nic()
1803 writeq(val64, &bar0->misc_control); in init_nic()
1804 val64 = readq(&bar0->pic_control2); in init_nic()
1806 writeq(val64, &bar0->pic_control2); in init_nic()
1810 writeq(val64, &bar0->tmac_avg_ipg); in init_nic()
1850 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_err_alarms() local
1854 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask); in en_dis_err_alarms()
1861 TXDMA_SM_INT, flag, &bar0->txdma_int_mask); in en_dis_err_alarms()
1866 &bar0->pfc_err_mask); in en_dis_err_alarms()
1870 TDA_PCIX_ERR, flag, &bar0->tda_err_mask); in en_dis_err_alarms()
1878 flag, &bar0->pcc_err_mask); in en_dis_err_alarms()
1881 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask); in en_dis_err_alarms()
1886 flag, &bar0->lso_err_mask); in en_dis_err_alarms()
1889 flag, &bar0->tpa_err_mask); in en_dis_err_alarms()
1891 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask); in en_dis_err_alarms()
1897 &bar0->mac_int_mask); in en_dis_err_alarms()
1901 flag, &bar0->mac_tmac_err_mask); in en_dis_err_alarms()
1907 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1910 flag, &bar0->xgxs_txgxs_err_mask); in en_dis_err_alarms()
1917 flag, &bar0->rxdma_int_mask); in en_dis_err_alarms()
1921 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask); in en_dis_err_alarms()
1925 &bar0->prc_pcix_err_mask); in en_dis_err_alarms()
1928 &bar0->rpa_err_mask); in en_dis_err_alarms()
1934 flag, &bar0->rda_err_mask); in en_dis_err_alarms()
1937 flag, &bar0->rti_err_mask); in en_dis_err_alarms()
1943 &bar0->mac_int_mask); in en_dis_err_alarms()
1950 flag, &bar0->mac_rmac_err_mask); in en_dis_err_alarms()
1956 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1958 &bar0->xgxs_rxgxs_err_mask); in en_dis_err_alarms()
1964 flag, &bar0->mc_int_mask); in en_dis_err_alarms()
1967 &bar0->mc_err_mask); in en_dis_err_alarms()
1988 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_able_nic_intrs() local
2008 &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2010 &bar0->gpio_int_mask); in en_dis_able_nic_intrs()
2012 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2018 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2030 writeq(0x0, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2036 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2045 writeq(0x0, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2051 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2055 temp64 = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2060 writeq(temp64, &bar0->general_int_mask); in en_dis_able_nic_intrs()
2062 nic->general_int_mask = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2076 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_pcc_quiescent() local
2077 u64 val64 = readq(&bar0->adapter_status); in verify_pcc_quiescent()
2118 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_xena_quiescence() local
2119 u64 val64 = readq(&bar0->adapter_status); in verify_xena_quiescence()
2184 struct XENA_dev_config __iomem *bar0 = sp->bar0; in fix_mac_address() local
2188 writeq(fix_mac[i++], &bar0->gpio_control); in fix_mac_address()
2190 (void) readq(&bar0->gpio_control); in fix_mac_address()
2209 struct XENA_dev_config __iomem *bar0 = nic->bar0; in start_nic() local
2221 &bar0->prc_rxd0_n[i]); in start_nic()
2223 val64 = readq(&bar0->prc_ctrl_n[i]); in start_nic()
2232 writeq(val64, &bar0->prc_ctrl_n[i]); in start_nic()
2237 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2239 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2243 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2245 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2254 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2256 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in start_nic()
2257 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2262 val64 = readq(&bar0->adapter_control); in start_nic()
2264 writeq(val64, &bar0->adapter_control); in start_nic()
2270 val64 = readq(&bar0->adapter_status); in start_nic()
2287 val64 = readq(&bar0->adapter_control); in start_nic()
2289 writeq(val64, &bar0->adapter_control); in start_nic()
2302 val64 = readq(&bar0->gpio_control); in start_nic()
2304 writeq(val64, &bar0->gpio_control); in start_nic()
2306 writeq(val64, (void __iomem *)bar0 + 0x2700); in start_nic()
2412 struct XENA_dev_config __iomem *bar0 = nic->bar0; in stop_nic() local
2423 val64 = readq(&bar0->adapter_control); in stop_nic()
2425 writeq(val64, &bar0->adapter_control); in stop_nic()
2766 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_msix() local
2778 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_poll_msix()
2792 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_inta() local
2812 writeq(0, &bar0->rx_traffic_mask); in s2io_poll_inta()
2813 readl(&bar0->rx_traffic_mask); in s2io_poll_inta()
2832 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_netpoll() local
2843 writeq(val64, &bar0->rx_traffic_int); in s2io_netpoll()
2844 writeq(val64, &bar0->tx_traffic_int); in s2io_netpoll()
3088 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_write() local
3094 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3096 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3105 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3107 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3114 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3116 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3134 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_read() local
3140 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3142 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3150 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3152 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3156 rval64 = readq(&bar0->mdio_control); in s2io_mdio_read()
3398 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_reset() local
3415 writeq(val64, &bar0->sw_reset); in s2io_reset()
3455 writeq(s2BIT(62), &bar0->txpic_int_reg); in s2io_reset()
3490 val64 = readq(&bar0->gpio_control); in s2io_reset()
3492 writeq(val64, &bar0->gpio_control); in s2io_reset()
3494 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_reset()
3502 val64 = readq(&bar0->pcc_err_reg); in s2io_reset()
3503 writeq(val64, &bar0->pcc_err_reg); in s2io_reset()
3522 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_swapper() local
3530 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3541 writeq(value[i], &bar0->swapper_ctrl); in s2io_set_swapper()
3542 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3555 valr = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3559 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3560 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3572 writeq((value[i] | valr), &bar0->swapper_ctrl); in s2io_set_swapper()
3573 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3574 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3586 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3607 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3631 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3633 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3639 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3653 struct XENA_dev_config __iomem *bar0 = nic->bar0; in wait_for_msix_trans() local
3658 val64 = readq(&bar0->xmsi_access); in wait_for_msix_trans()
3674 struct XENA_dev_config __iomem *bar0 = nic->bar0; in restore_xmsi_data() local
3683 writeq(nic->msix_info[i].addr, &bar0->xmsi_address); in restore_xmsi_data()
3684 writeq(nic->msix_info[i].data, &bar0->xmsi_data); in restore_xmsi_data()
3686 writeq(val64, &bar0->xmsi_access); in restore_xmsi_data()
3695 struct XENA_dev_config __iomem *bar0 = nic->bar0; in store_xmsi_data() local
3706 writeq(val64, &bar0->xmsi_access); in store_xmsi_data()
3712 addr = readq(&bar0->xmsi_address); in store_xmsi_data()
3713 data = readq(&bar0->xmsi_data); in store_xmsi_data()
3723 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_enable_msi_x() local
3767 rx_mat = readq(&bar0->rx_mat); in s2io_enable_msi_x()
3775 writeq(rx_mat, &bar0->rx_mat); in s2io_enable_msi_x()
3776 readq(&bar0->rx_mat); in s2io_enable_msi_x()
3820 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_test_msi() local
3835 saved64 = val64 = readq(&bar0->scheduled_int_ctrl); in s2io_test_msi()
3839 writeq(val64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
3854 writeq(saved64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
4204 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_ring_handle() local
4213 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_msix_ring_handle()
4232 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_fifo_handle() local
4239 reason = readq(&bar0->general_int_status); in s2io_msix_fifo_handle()
4245 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4251 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_msix_fifo_handle()
4256 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4257 readl(&bar0->general_int_status); in s2io_msix_fifo_handle()
4266 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_txpic_intr_handle() local
4269 val64 = readq(&bar0->pic_int_status); in s2io_txpic_intr_handle()
4271 val64 = readq(&bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4280 writeq(val64, &bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4281 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4284 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4286 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4288 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4290 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4292 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4301 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4304 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4307 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4310 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4313 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4316 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4318 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4321 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4360 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_handle_errors() local
4388 val64 = readq(&bar0->mac_rmac_err_reg); in s2io_handle_errors()
4389 writeq(val64, &bar0->mac_rmac_err_reg); in s2io_handle_errors()
4395 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source, in s2io_handle_errors()
4400 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg, in s2io_handle_errors()
4406 val64 = readq(&bar0->ring_bump_counter1); in s2io_handle_errors()
4413 val64 = readq(&bar0->ring_bump_counter2); in s2io_handle_errors()
4421 val64 = readq(&bar0->txdma_int_status); in s2io_handle_errors()
4427 &bar0->pfc_err_reg, in s2io_handle_errors()
4431 &bar0->pfc_err_reg, in s2io_handle_errors()
4440 &bar0->tda_err_reg, in s2io_handle_errors()
4444 &bar0->tda_err_reg, in s2io_handle_errors()
4454 &bar0->pcc_err_reg, in s2io_handle_errors()
4458 &bar0->pcc_err_reg, in s2io_handle_errors()
4465 &bar0->tti_err_reg, in s2io_handle_errors()
4469 &bar0->tti_err_reg, in s2io_handle_errors()
4477 &bar0->lso_err_reg, in s2io_handle_errors()
4481 &bar0->lso_err_reg, in s2io_handle_errors()
4488 &bar0->tpa_err_reg, in s2io_handle_errors()
4492 &bar0->tpa_err_reg, in s2io_handle_errors()
4499 &bar0->sm_err_reg, in s2io_handle_errors()
4504 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4507 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4513 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4517 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4520 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4524 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4528 val64 = readq(&bar0->rxdma_int_status); in s2io_handle_errors()
4534 &bar0->rc_err_reg, in s2io_handle_errors()
4539 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg, in s2io_handle_errors()
4544 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4550 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4556 &bar0->rpa_err_reg, in s2io_handle_errors()
4560 &bar0->rpa_err_reg, in s2io_handle_errors()
4570 &bar0->rda_err_reg, in s2io_handle_errors()
4577 &bar0->rda_err_reg, in s2io_handle_errors()
4583 &bar0->rti_err_reg, in s2io_handle_errors()
4587 &bar0->rti_err_reg, in s2io_handle_errors()
4591 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4594 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4600 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4604 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4607 &bar0->xgxs_rxgxs_err_reg, in s2io_handle_errors()
4612 val64 = readq(&bar0->mc_int_status); in s2io_handle_errors()
4615 &bar0->mc_err_reg, in s2io_handle_errors()
4621 writeq(val64, &bar0->mc_err_reg); in s2io_handle_errors()
4662 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_isr() local
4685 reason = readq(&bar0->general_int_status); in s2io_isr()
4692 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_isr()
4697 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); in s2io_isr()
4698 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4699 readl(&bar0->rx_traffic_int); in s2io_isr()
4708 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4723 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_isr()
4741 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_isr()
4742 readl(&bar0->general_int_status); in s2io_isr()
4759 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_updt_stats() local
4767 writeq(val64, &bar0->stat_cfg); in s2io_updt_stats()
4770 val64 = readq(&bar0->stat_cfg); in s2io_updt_stats()
4886 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_multicast() local
4896 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4898 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4902 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4904 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4913 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4915 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4919 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4921 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4931 add = &bar0->mac_cfg; in s2io_set_multicast()
4932 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4935 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4937 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4941 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4943 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4947 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4953 add = &bar0->mac_cfg; in s2io_set_multicast()
4954 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4957 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4959 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4963 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4965 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4969 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4991 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4993 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4998 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5001 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5021 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
5023 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
5028 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5031 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5118 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_add_mac() local
5121 &bar0->rmac_addr_data0_mem); in do_s2io_add_mac()
5125 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_add_mac()
5128 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_add_mac()
5164 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_read_unicast_mc() local
5169 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_read_unicast_mc()
5172 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_read_unicast_mc()
5178 tmp64 = readq(&bar0->rmac_addr_data0_mem); in do_s2io_read_unicast_mc()
5370 reg = readq(sp->bar0 + i); in s2io_ethtool_gregs()
5380 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_led() local
5386 val64 = readq(&bar0->gpio_control); in s2io_set_led()
5392 writeq(val64, &bar0->gpio_control); in s2io_set_led()
5394 val64 = readq(&bar0->adapter_control); in s2io_set_led()
5400 writeq(val64, &bar0->adapter_control); in s2io_set_led()
5421 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_set_led() local
5425 u64 val64 = readq(&bar0->adapter_control); in s2io_ethtool_set_led()
5434 sp->adapt_ctrl_org = readq(&bar0->gpio_control); in s2io_ethtool_set_led()
5447 writeq(sp->adapt_ctrl_org, &bar0->gpio_control); in s2io_ethtool_set_led()
5494 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_getpause_data() local
5496 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_getpause_data()
5520 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_setpause_data() local
5522 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5531 writeq(val64, &bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5556 struct XENA_dev_config __iomem *bar0 = sp->bar0; in read_eeprom() local
5564 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in read_eeprom()
5567 val64 = readq(&bar0->i2c_control); in read_eeprom()
5582 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5584 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5586 val64 = readq(&bar0->spi_control); in read_eeprom()
5591 *data = readq(&bar0->spi_data); in read_eeprom()
5622 struct XENA_dev_config __iomem *bar0 = sp->bar0; in write_eeprom() local
5630 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in write_eeprom()
5633 val64 = readq(&bar0->i2c_control); in write_eeprom()
5646 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data); in write_eeprom()
5651 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5653 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5655 val64 = readq(&bar0->spi_control); in write_eeprom()
5841 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_register_test() local
5845 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_register_test()
5851 val64 = readq(&bar0->rmac_pause_cfg); in s2io_register_test()
5857 val64 = readq(&bar0->rx_queue_cfg); in s2io_register_test()
5867 val64 = readq(&bar0->xgxs_efifo_cfg); in s2io_register_test()
5874 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5875 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5882 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5883 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
6046 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_link_test() local
6049 val64 = readq(&bar0->adapter_status); in s2io_link_test()
6073 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_rldram_test() local
6077 val64 = readq(&bar0->adapter_control); in s2io_rldram_test()
6079 writeq(val64, &bar0->adapter_control); in s2io_rldram_test()
6081 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6083 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6085 val64 = readq(&bar0->mc_rldram_mrs); in s2io_rldram_test()
6087 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6090 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6096 writeq(val64, &bar0->mc_rldram_test_d0); in s2io_rldram_test()
6101 writeq(val64, &bar0->mc_rldram_test_d1); in s2io_rldram_test()
6106 writeq(val64, &bar0->mc_rldram_test_d2); in s2io_rldram_test()
6109 writeq(val64, &bar0->mc_rldram_test_add); in s2io_rldram_test()
6114 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6117 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6127 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6130 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6139 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6149 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6644 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_change_mtu() local
6647 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in s2io_change_mtu()
6664 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_set_link() local
6687 val64 = readq(&bar0->adapter_status); in s2io_set_link()
6689 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { in s2io_set_link()
6691 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6693 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6696 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6698 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6699 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6702 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6712 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6714 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6719 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6721 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6722 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6725 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6727 writeq(val64, &bar0->adapter_control); in s2io_set_link()
7006 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_card_down() local
7051 val64 = readq(&bar0->adapter_status); in do_s2io_card_down()
7601 struct XENA_dev_config __iomem *bar0 = nic->bar0; in rts_ds_steer() local
7608 writeq(val64, &bar0->rts_ds_mem_data); in rts_ds_steer()
7614 writeq(val64, &bar0->rts_ds_mem_ctrl); in rts_ds_steer()
7616 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, in rts_ds_steer()
7661 struct XENA_dev_config __iomem *bar0 = NULL; in s2io_init_nic() local
7840 sp->bar0 = pci_ioremap_bar(pdev, 0); in s2io_init_nic()
7841 if (!sp->bar0) { in s2io_init_nic()
7937 bar0 = sp->bar0; in s2io_init_nic()
7940 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_init_nic()
7941 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_init_nic()
7944 tmp64 = readq(&bar0->rmac_addr_data0_mem); in s2io_init_nic()
8006 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8008 writeq(val64, &bar0->gpio_control); in s2io_init_nic()
8010 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_init_nic()
8011 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8123 iounmap(sp->bar0); in s2io_init_nic()
8161 iounmap(sp->bar0); in s2io_rem_nic()