169 static inline void bw32(const struct b44 *bp,  in bw32()  function
203 	bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |  in __b44_cam_read()
229 	bw32(bp, B44_CAM_DATA_LO, val);  in __b44_cam_write()
233 	bw32(bp, B44_CAM_DATA_HI, val);  in __b44_cam_write()
234 	bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |  in __b44_cam_write()
241 	bw32(bp, B44_IMASK, 0);  in __b44_disable_ints()
254 	bw32(bp, B44_IMASK, bp->imask);  in b44_enable_ints()
261 	bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);  in __b44_readphy()
262 	bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |  in __b44_readphy()
275 	bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);  in __b44_writephy()
276 	bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |  in __b44_writephy()
370 	bw32(bp, B44_RXCONFIG, val);  in __b44_set_flow_ctrl()
378 	bw32(bp, B44_MAC_FLOW, val);  in __b44_set_flow_ctrl()
546 			bw32(bp, B44_TX_CTRL, val);  in b44_check_phy()
574 			bw32(bp, B44_TX_CTRL, val);  in b44_check_phy()
645 	bw32(bp, B44_GPTIMER, 0);  in b44_tx()
856 	bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));  in b44_rx()
942 		bw32(bp, B44_ISTAT, istat);  in b44_interrupt()
1037 	bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));  in b44_start_xmit()
1039 		bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));  in b44_start_xmit()
1268 	bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);  in b44_clear_stats()
1287 		bw32(bp, B44_RCV_LAZY, 0);  in b44_chip_reset()
1288 		bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);  in b44_chip_reset()
1290 		bw32(bp, B44_DMATX_CTRL, 0);  in b44_chip_reset()
1296 		bw32(bp, B44_DMARX_CTRL, 0);  in b44_chip_reset()
1311 		bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |  in b44_chip_reset()
1317 		bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |  in b44_chip_reset()
1329 		bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);  in b44_chip_reset()
1336 			bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));  in b44_chip_reset()
1352 	bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);  in b44_halt()
1364 	bw32(bp, B44_CAM_CTRL, 0);  in __b44_set_mac_addr()
1370 		bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);  in __b44_set_mac_addr()
1414 	bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);  in b44_init_hw()
1415 	bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));  in b44_init_hw()
1421 	bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);  in b44_init_hw()
1422 	bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);  in b44_init_hw()
1424 	bw32(bp, B44_TX_WMARK, 56); /* XXX magic */  in b44_init_hw()
1426 		bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |  in b44_init_hw()
1429 		bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);  in b44_init_hw()
1430 		bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);  in b44_init_hw()
1431 		bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |  in b44_init_hw()
1433 		bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);  in b44_init_hw()
1435 		bw32(bp, B44_DMARX_PTR, bp->rx_pending);  in b44_init_hw()
1438 		bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);  in b44_init_hw()
1442 	bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));  in b44_init_hw()
1505 		bw32(bp, B44_FILT_ADDR, table_offset + i);  in bwfilter_table()
1506 		bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);  in bwfilter_table()
1588 	bw32(bp, B44_WKUP_LEN, val);  in b44_setup_pseudo_magicp()
1592 	bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);  in b44_setup_pseudo_magicp()
1602 		bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);  in b44_setup_wol_pci()
1615 	bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);  in b44_setup_wol()
1619 		bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);  in b44_setup_wol()
1625 		bw32(bp, B44_ADDR_LO, val);  in b44_setup_wol()
1629 		bw32(bp, B44_ADDR_HI, val);  in b44_setup_wol()
1632 		bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);  in b44_setup_wol()
1743 		bw32(bp, B44_RXCONFIG, val);  in __b44_set_rx_mode()
1759 		bw32(bp, B44_RXCONFIG, val);  in __b44_set_rx_mode()
1761 	        bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);  in __b44_set_rx_mode()
2241 		bw32(bp, B44_TX_CTRL, val);  in b44_adjust_link()