406 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value)  in ag71xx_wr()  function
572 	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,  in ag71xx_mdio_mii_read()
575 	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);  in ag71xx_mdio_mii_read()
583 	ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0);  in ag71xx_mdio_mii_read()
599 	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,  in ag71xx_mdio_mii_write()
601 	ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);  in ag71xx_mdio_mii_write()
662 	ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);  in ag71xx_mdio_reset()
665 	ag71xx_wr(ag, AG71XX_REG_MII_CFG, t);  in ag71xx_mdio_reset()
747 	ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);  in ag71xx_hw_stop()
748 	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);  in ag71xx_hw_stop()
749 	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);  in ag71xx_hw_stop()
825 			ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);  in ag71xx_tx_packets()
874 	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);  in ag71xx_dma_reset()
875 	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);  in ag71xx_dma_reset()
883 	ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);  in ag71xx_dma_reset()
884 	ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);  in ag71xx_dma_reset()
888 		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);  in ag71xx_dma_reset()
889 		ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);  in ag71xx_dma_reset()
893 	ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);  in ag71xx_dma_reset()
894 	ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);  in ag71xx_dma_reset()
916 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);  in ag71xx_hw_setup()
922 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);  in ag71xx_hw_setup()
925 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);  in ag71xx_hw_setup()
926 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);  in ag71xx_hw_setup()
927 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);  in ag71xx_hw_setup()
928 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);  in ag71xx_hw_setup()
929 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);  in ag71xx_hw_setup()
944 	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);  in ag71xx_hw_set_macaddr()
947 	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);  in ag71xx_hw_set_macaddr()
975 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL,  in ag71xx_fast_reset()
978 	ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);  in ag71xx_fast_reset()
979 	ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);  in ag71xx_fast_reset()
980 	ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);  in ag71xx_fast_reset()
988 	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);  in ag71xx_hw_start()
991 	ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);  in ag71xx_hw_start()
1012 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);  in ag71xx_mac_config()
1139 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);  in ag71xx_mac_link_up()
1140 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);  in ag71xx_mac_link_up()
1141 	ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);  in ag71xx_mac_link_up()
1150 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1);  in ag71xx_mac_link_up()
1441 	ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);  in ag71xx_hw_enable()
1442 	ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);  in ag71xx_hw_enable()
1479 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);  in ag71xx_open()
1612 	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);  in ag71xx_hard_start_xmit()
1691 		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);  in ag71xx_rx_packets()
1758 		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);  in ag71xx_poll()
1762 		ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);  in ag71xx_poll()
1810 			ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);  in ag71xx_interrupt()
1814 			ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);  in ag71xx_interrupt()
1833 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL,  in ag71xx_change_mtu()
1978 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);  in ag71xx_probe()