210 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )  in bmwrite()  function
245 		bmwrite(dev, MIFCSR, 0);  in bmac_mif_readbits()
249 		bmwrite(dev, MIFCSR, 1);  in bmac_mif_readbits()
252 	bmwrite(dev, MIFCSR, 0);  in bmac_mif_readbits()
254 	bmwrite(dev, MIFCSR, 1);  in bmac_mif_readbits()
266 		bmwrite(dev, MIFCSR, b);  in bmac_mif_writebits()
268 		bmwrite(dev, MIFCSR, b|1);  in bmac_mif_writebits()
278 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_read()
283 	bmwrite(dev, MIFCSR, 2);  in bmac_mif_read()
285 	bmwrite(dev, MIFCSR, 1);  in bmac_mif_read()
288 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_read()
296 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_write()
316 	bmwrite(dev, RXRST, RxResetValue);  in bmac_init_registers()
317 	bmwrite(dev, TXRST, TxResetBit);  in bmac_init_registers()
329 		bmwrite(dev, XCVRIF, regValue);  in bmac_init_registers()
333 	bmwrite(dev, RSEED, (unsigned short)0x1968);  in bmac_init_registers()
337 	bmwrite(dev, XIFC, regValue);  in bmac_init_registers()
342 	bmwrite(dev, NCCNT, 0);  in bmac_init_registers()
343 	bmwrite(dev, NTCNT, 0);  in bmac_init_registers()
344 	bmwrite(dev, EXCNT, 0);  in bmac_init_registers()
345 	bmwrite(dev, LTCNT, 0);  in bmac_init_registers()
348 	bmwrite(dev, FRCNT, 0);  in bmac_init_registers()
349 	bmwrite(dev, LECNT, 0);  in bmac_init_registers()
350 	bmwrite(dev, AECNT, 0);  in bmac_init_registers()
351 	bmwrite(dev, FECNT, 0);  in bmac_init_registers()
352 	bmwrite(dev, RXCV, 0);  in bmac_init_registers()
355 	bmwrite(dev, TXTH, 4);	/* 4 octets before tx starts */  in bmac_init_registers()
357 	bmwrite(dev, TXFIFOCSR, 0);	/* first disable txFIFO */  in bmac_init_registers()
358 	bmwrite(dev, TXFIFOCSR, TxFIFOEnable );  in bmac_init_registers()
361 	bmwrite(dev, RXFIFOCSR, 0);	/* first disable rxFIFO */  in bmac_init_registers()
362 	bmwrite(dev, RXFIFOCSR, RxFIFOEnable );  in bmac_init_registers()
369 	bmwrite(dev, BHASH3, bp->hash_table_mask[0]); 	/* bits 15 - 0 */  in bmac_init_registers()
370 	bmwrite(dev, BHASH2, bp->hash_table_mask[1]); 	/* bits 31 - 16 */  in bmac_init_registers()
371 	bmwrite(dev, BHASH1, bp->hash_table_mask[2]); 	/* bits 47 - 32 */  in bmac_init_registers()
372 	bmwrite(dev, BHASH0, bp->hash_table_mask[3]); 	/* bits 63 - 48 */  in bmac_init_registers()
375 	bmwrite(dev, MADD0, *pWord16++);  in bmac_init_registers()
376 	bmwrite(dev, MADD1, *pWord16++);  in bmac_init_registers()
377 	bmwrite(dev, MADD2, *pWord16);  in bmac_init_registers()
379 	bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);  in bmac_init_registers()
381 	bmwrite(dev, INTDISABLE, EnableNormal);  in bmac_init_registers()
388 	bmwrite(dev, INTDISABLE, DisableAll);
394 	bmwrite(dev, INTDISABLE, EnableNormal);
410 	bmwrite(dev, TXCFG, oldConfig | TxMACEnable );  in bmac_start_chip()
414 	bmwrite(dev, RXCFG, oldConfig | RxMACEnable );  in bmac_start_chip()
478 		bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_suspend()
480        		bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_suspend()
481 		bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */  in bmac_suspend()
537 	bmwrite(dev, MADD0, *pWord16++);  in bmac_set_address()
538 	bmwrite(dev, MADD1, *pWord16++);  in bmac_set_address()
539 	bmwrite(dev, MADD2, *pWord16);  in bmac_set_address()
904 	bmwrite(dev, RXCFG, rx_cfg);  in bmac_rx_off()
921 	bmwrite(dev, RXRST, RxResetValue);  in bmac_rx_on()
922 	bmwrite(dev, RXFIFOCSR, 0);	/* first disable rxFIFO */  in bmac_rx_on()
923 	bmwrite(dev, RXFIFOCSR, RxFIFOEnable );  in bmac_rx_on()
924 	bmwrite(dev, RXCFG, rx_cfg );  in bmac_rx_on()
931 	bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */  in bmac_update_hash_table_mask()
932 	bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */  in bmac_update_hash_table_mask()
933 	bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */  in bmac_update_hash_table_mask()
934 	bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */  in bmac_update_hash_table_mask()
988 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1018 		bmwrite(dev, BHASH0, 0xffff);  in bmac_set_multicast()
1019 		bmwrite(dev, BHASH1, 0xffff);  in bmac_set_multicast()
1020 		bmwrite(dev, BHASH2, 0xffff);  in bmac_set_multicast()
1021 		bmwrite(dev, BHASH3, 0xffff);  in bmac_set_multicast()
1025 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1031 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1038 		bmwrite(dev, BHASH0, hash_table[0]);  in bmac_set_multicast()
1039 		bmwrite(dev, BHASH1, hash_table[1]);  in bmac_set_multicast()
1040 		bmwrite(dev, BHASH2, hash_table[2]);  in bmac_set_multicast()
1041 		bmwrite(dev, BHASH3, hash_table[3]);  in bmac_set_multicast()
1093 	bmwrite(dev, SROMCSR, ChipSelect | Clk);  in bmac_clock_out_bit()
1100 	bmwrite(dev, SROMCSR, ChipSelect);  in bmac_clock_out_bit()
1114 	bmwrite(dev, SROMCSR, data | ChipSelect  );  in bmac_clock_in_bit()
1117 	bmwrite(dev, SROMCSR, data | ChipSelect | Clk );  in bmac_clock_in_bit()
1120 	bmwrite(dev, SROMCSR, data | ChipSelect);  in bmac_clock_in_bit()
1128 	bmwrite(dev, SROMCSR, 0);  in reset_and_select_srom()
1156 	bmwrite(dev, SROMCSR, 0);  in read_srom()
1207 	bmwrite(dev, INTDISABLE, EnableNormal);  in bmac_reset_and_enable()
1286 	bmwrite(dev, INTDISABLE, DisableAll);  in bmac_probe()
1294 	bmwrite(dev, INTDISABLE, DisableAll);  in bmac_probe()
1399 	bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_close()
1402 	bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_close()
1404 	bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */  in bmac_close()
1494 	bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_tx_timeout()
1496 	bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_tx_timeout()
1533 	bmwrite(dev, RXCFG, oldConfig | RxMACEnable );  in bmac_tx_timeout()
1535 	bmwrite(dev, TXCFG, oldConfig | TxMACEnable );  in bmac_tx_timeout()