Lines Matching refs:REGA
165 #define REGA(a) (*( AREG = (a), &DREG )) macro
360 REGA(CSR0) = CSR0_STOP; in lance_probe()
425 REGA(CSR0) = CSR0_STOP; in lance_open()
430 REGA(CSR0) = CSR0_INIT; in lance_open()
503 REGA(CSR1) = dvma_vtob(&(MEM->init)); in lance_init_ring()
504 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16; in lance_init_ring()
507 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON; in lance_init_ring()
509 REGA(CSR3) = CSR3_BSWP; in lance_init_ring()
539 REGA(CSR3) = CSR3_BSWP; in lance_start_xmit()
561 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_start_xmit()
591 REGA( CSR0 ) = CSR0_STOP; in lance_start_xmit()
593 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT; in lance_start_xmit()
637 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; in lance_start_xmit()
709 REGA(CSR0) = CSR0_STOP; in lance_interrupt()
710 REGA(CSR3) = CSR3_BSWP; in lance_interrupt()
712 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()
747 REGA(CSR0) = CSR0_STOP; in lance_interrupt()
748 REGA(CSR3) = CSR3_BSWP; in lance_interrupt()
750 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()
758 REGA(CSR0) = CSR0_INEA; in lance_interrupt()
902 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */ in set_multicast_list()
912 REGA( CSR8+i ) = multicast_table[i]; in set_multicast_list()
913 REGA( CSR15 ) = 0; /* Unset promiscuous mode */ in set_multicast_list()
920 REGA( CSR3 ) = CSR3_BSWP; in set_multicast_list()
923 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()