226 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)  in mt7530_write()  function
305 	mt7530_write(priv, MT7530_ATC, val);  in mt7530_fdb_cmd()
379 		mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);  in mt7530_fdb_write()
435 		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),  in mt7530_pad_clk_setup()
531 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
536 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
540 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
545 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
551 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
559 		mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
565 		mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
572 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
579 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
582 	mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);  in mt7531_pll_setup()
585 	mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);  in mt7531_pll_setup()
590 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
594 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
603 	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);  in mt7530_mib_reset()
604 	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);  in mt7530_mib_reset()
900 		mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);  in mt7530_setup_port5()
920 		mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);  in mt7530_setup_port5()
929 		mt7530_write(priv, MT7530_P5RGMIITXCR,  in mt7530_setup_port5()
933 		mt7530_write(priv, MT7530_IO_DRV_CR,  in mt7530_setup_port5()
937 	mt7530_write(priv, MT7530_MHWTRAP, val);  in mt7530_setup_port5()
962 	mt7530_write(priv, MT7530_PVC_P(port),  in mt753x_cpu_port_enable()
975 	mt7530_write(priv, MT7530_PCR_P(port),  in mt753x_cpu_port_enable()
1117 		mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),  in mt7530_port_set_vlan_unaware()
1119 		mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG  in mt7530_port_set_vlan_unaware()
1258 	mt7530_write(priv, MT7530_VTCR, val);  in mt7530_vlan_cmd()
1323 	mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_hw_vlan_add()
1368 		mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_hw_vlan_del()
1370 		mt7530_write(priv, MT7530_VAWD1, 0);  in mt7530_hw_vlan_del()
1371 		mt7530_write(priv, MT7530_VAWD2, 0);  in mt7530_hw_vlan_del()
1489 	mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);  in mt753x_port_mirror_add()
1499 	mt7530_write(priv, MT7530_PCR_P(port), val);  in mt753x_port_mirror_add()
1518 	mt7530_write(priv, MT7530_PCR_P(port), val);  in mt753x_port_mirror_del()
1523 		mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);  in mt753x_port_mirror_del()
1609 	mt7530_write(priv, MT7530_SYS_CTRL,  in mt7530_setup()
1617 	mt7530_write(priv, MT7530_MHWTRAP, val);  in mt7530_setup()
1733 	mt7530_write(priv, MT7530_SYS_CTRL,  in mt7531_setup()
1949 	mt7530_write(priv, MT7531_CLKGEN_CTRL, val);  in mt7531_rgmii_setup()
2002 	mt7530_write(priv, MT7531_SGMII_MODE(port), val);  in mt7531_sgmii_link_up_force()
2028 	mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);  in mt7531_sgmii_setup_mode_force()
2039 	mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);  in mt7531_sgmii_setup_mode_force()
2067 	mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);  in mt7531_sgmii_setup_mode_an()
2081 		mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);  in mt7531_sgmii_restart_an()
2192 		mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);  in mt753x_phylink_mac_config()
2303 	mt7530_write(priv, MT7530_PMCR_P(port),  in mt7531_cpu_port_config()