1223 		u32 reg_fdcbt, reg_ctrl2;  in flexcan_set_bittiming_cbt()  local
1259 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_set_bittiming_cbt()
1260 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1262 			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1264 		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);  in flexcan_set_bittiming_cbt()
1265 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_set_bittiming_cbt()
1328 	u32 reg_ctrl2;  in flexcan_ram_init()  local
1338 	reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_ram_init()
1339 	reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1340 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1351 	reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1352 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1364 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;  in flexcan_chip_start()  local
1473 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1474 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;  in flexcan_chip_start()
1475 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1554 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1555 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1556 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1574 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1575 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()