Lines Matching refs:nandc
182 #define nandc_set_read_loc(nandc, reg, offset, size, is_last) \ argument
183 nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
192 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) argument
472 static void free_bam_transaction(struct qcom_nand_controller *nandc) in free_bam_transaction() argument
474 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
476 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
481 alloc_bam_transaction(struct qcom_nand_controller *nandc) in alloc_bam_transaction() argument
485 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
494 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
517 static void clear_bam_transaction(struct qcom_nand_controller *nandc) in clear_bam_transaction() argument
519 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
521 if (!nandc->props->is_bam) in clear_bam_transaction()
535 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
537 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
573 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset) in nandc_read() argument
575 return ioread32(nandc->base + offset); in nandc_read()
578 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset, in nandc_write() argument
581 iowrite32(val, nandc->base + offset); in nandc_write()
584 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, in nandc_read_buffer_sync() argument
587 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
591 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
593 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
596 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
598 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
648 static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, in nandc_set_reg() argument
651 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
664 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in set_address() local
669 nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column); in set_address()
670 nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff); in set_address()
683 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in update_rw_regs() local
709 nandc_set_reg(nandc, NAND_FLASH_CMD, cmd); in update_rw_regs()
710 nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0); in update_rw_regs()
711 nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1); in update_rw_regs()
712 nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg); in update_rw_regs()
713 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); in update_rw_regs()
714 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in update_rw_regs()
715 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in update_rw_regs()
716 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in update_rw_regs()
719 nandc_set_read_loc(nandc, 0, 0, host->use_ecc ? in update_rw_regs()
728 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, in prepare_bam_async_desc() argument
736 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
744 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
750 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
765 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
767 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
779 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
780 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
788 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
793 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
807 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_cmd() argument
814 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
822 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
824 reg_buf_dma_addr(nandc, in prep_bam_dma_desc_cmd()
828 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
847 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
862 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_data() argument
867 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
883 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
893 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, in prep_adm_dma_desc() argument
920 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
931 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
932 slave_conf.slave_id = nandc->data_crci; in prep_adm_dma_desc()
935 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
936 slave_conf.slave_id = nandc->cmd_crci; in prep_adm_dma_desc()
939 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
941 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
945 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
947 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
954 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
971 static int read_reg_dma(struct qcom_nand_controller *nandc, int first, in read_reg_dma() argument
977 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
978 nandc->reg_read_pos += num_regs; in read_reg_dma()
981 first = dev_cmd_reg_addr(nandc, first); in read_reg_dma()
983 if (nandc->props->is_bam) in read_reg_dma()
984 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, in read_reg_dma()
990 return prep_adm_dma_desc(nandc, true, first, vaddr, in read_reg_dma()
1002 static int write_reg_dma(struct qcom_nand_controller *nandc, int first, in write_reg_dma() argument
1006 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1022 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); in write_reg_dma()
1025 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); in write_reg_dma()
1027 if (nandc->props->is_bam) in write_reg_dma()
1028 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, in write_reg_dma()
1034 return prep_adm_dma_desc(nandc, false, first, vaddr, in write_reg_dma()
1047 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1050 if (nandc->props->is_bam) in read_data_dma()
1051 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); in read_data_dma()
1053 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1065 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1068 if (nandc->props->is_bam) in write_data_dma()
1069 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); in write_data_dma()
1071 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1078 static void config_nand_page_read(struct qcom_nand_controller *nandc) in config_nand_page_read() argument
1080 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_read()
1081 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_read()
1082 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); in config_nand_page_read()
1083 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); in config_nand_page_read()
1084 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, in config_nand_page_read()
1093 config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc) in config_nand_cw_read() argument
1095 if (nandc->props->is_bam) in config_nand_cw_read()
1096 write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, in config_nand_cw_read()
1099 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1100 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1103 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); in config_nand_cw_read()
1104 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, in config_nand_cw_read()
1107 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1116 config_nand_single_cw_page_read(struct qcom_nand_controller *nandc, in config_nand_single_cw_page_read() argument
1119 config_nand_page_read(nandc); in config_nand_single_cw_page_read()
1120 config_nand_cw_read(nandc, use_ecc); in config_nand_single_cw_page_read()
1127 static void config_nand_page_write(struct qcom_nand_controller *nandc) in config_nand_page_write() argument
1129 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_write()
1130 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_write()
1131 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, in config_nand_page_write()
1139 static void config_nand_cw_write(struct qcom_nand_controller *nandc) in config_nand_cw_write() argument
1141 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1142 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1144 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1146 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in config_nand_cw_write()
1147 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1159 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_param() local
1166 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE); in nandc_param()
1167 nandc_set_reg(nandc, NAND_ADDR0, 0); in nandc_param()
1168 nandc_set_reg(nandc, NAND_ADDR1, 0); in nandc_param()
1169 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE in nandc_param()
1173 nandc_set_reg(nandc, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES in nandc_param()
1180 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); in nandc_param()
1183 nandc_set_reg(nandc, NAND_DEV_CMD_VLD, in nandc_param()
1184 (nandc->vld & ~READ_START_VLD)); in nandc_param()
1185 nandc_set_reg(nandc, NAND_DEV_CMD1, in nandc_param()
1186 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in nandc_param()
1189 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in nandc_param()
1191 nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in nandc_param()
1192 nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in nandc_param()
1193 nandc_set_read_loc(nandc, 0, 0, 512, 1); in nandc_param()
1195 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); in nandc_param()
1196 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1198 nandc->buf_count = 512; in nandc_param()
1199 memset(nandc->data_buffer, 0xff, nandc->buf_count); in nandc_param()
1201 config_nand_single_cw_page_read(nandc, false); in nandc_param()
1203 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in nandc_param()
1204 nandc->buf_count, 0); in nandc_param()
1207 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); in nandc_param()
1208 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1217 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in erase_block() local
1219 nandc_set_reg(nandc, NAND_FLASH_CMD, in erase_block()
1221 nandc_set_reg(nandc, NAND_ADDR0, page_addr); in erase_block()
1222 nandc_set_reg(nandc, NAND_ADDR1, 0); in erase_block()
1223 nandc_set_reg(nandc, NAND_DEV0_CFG0, in erase_block()
1225 nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw); in erase_block()
1226 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in erase_block()
1227 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in erase_block()
1228 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in erase_block()
1230 write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in erase_block()
1231 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in erase_block()
1232 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in erase_block()
1234 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1236 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in erase_block()
1237 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1246 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_id() local
1251 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID); in read_id()
1252 nandc_set_reg(nandc, NAND_ADDR0, column); in read_id()
1253 nandc_set_reg(nandc, NAND_ADDR1, 0); in read_id()
1254 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, in read_id()
1255 nandc->props->is_bam ? 0 : DM_EN); in read_id()
1256 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in read_id()
1258 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); in read_id()
1259 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in read_id()
1261 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); in read_id()
1270 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in reset() local
1272 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE); in reset()
1273 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in reset()
1275 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1276 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1278 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in reset()
1284 static int submit_descs(struct qcom_nand_controller *nandc) in submit_descs() argument
1288 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1291 if (nandc->props->is_bam) { in submit_descs()
1293 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1299 r = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1306 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1313 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1316 if (nandc->props->is_bam) { in submit_descs()
1325 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1326 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1327 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1333 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1340 static void free_descs(struct qcom_nand_controller *nandc) in free_descs() argument
1344 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in free_descs()
1347 if (nandc->props->is_bam) in free_descs()
1348 dma_unmap_sg(nandc->dev, desc->bam_sgl, in free_descs()
1351 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in free_descs()
1359 static void clear_read_regs(struct qcom_nand_controller *nandc) in clear_read_regs() argument
1361 nandc->reg_read_pos = 0; in clear_read_regs()
1362 nandc_read_buffer_sync(nandc, false); in clear_read_regs()
1368 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in pre_command() local
1370 nandc->buf_count = 0; in pre_command()
1371 nandc->buf_start = 0; in pre_command()
1375 clear_read_regs(nandc); in pre_command()
1379 clear_bam_transaction(nandc); in pre_command()
1390 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_erase_write_errors() local
1396 nandc_read_buffer_sync(nandc, true); in parse_erase_write_errors()
1399 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in parse_erase_write_errors()
1414 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in post_command() local
1418 nandc_read_buffer_sync(nandc, true); in post_command()
1419 memcpy(nandc->data_buffer, nandc->reg_read_buf, in post_command()
1420 nandc->buf_count); in post_command()
1442 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_command() local
1455 nandc->buf_count = 4; in qcom_nandc_command()
1492 dev_err(nandc->dev, "failure executing command %d\n", in qcom_nandc_command()
1494 free_descs(nandc); in qcom_nandc_command()
1499 ret = submit_descs(nandc); in qcom_nandc_command()
1501 dev_err(nandc->dev, in qcom_nandc_command()
1506 free_descs(nandc); in qcom_nandc_command()
1569 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in check_flash_errors() local
1572 nandc_read_buffer_sync(nandc, true); in check_flash_errors()
1575 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1590 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_cw_raw() local
1598 clear_bam_transaction(nandc); in qcom_nandc_read_cw_raw()
1601 config_nand_page_read(nandc); in qcom_nandc_read_cw_raw()
1616 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1617 nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0); in qcom_nandc_read_cw_raw()
1620 nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0); in qcom_nandc_read_cw_raw()
1623 nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0); in qcom_nandc_read_cw_raw()
1626 nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1); in qcom_nandc_read_cw_raw()
1629 config_nand_cw_read(nandc, false); in qcom_nandc_read_cw_raw()
1631 read_data_dma(nandc, reg_off, data_buf, data_size1, 0); in qcom_nandc_read_cw_raw()
1634 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); in qcom_nandc_read_cw_raw()
1637 read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); in qcom_nandc_read_cw_raw()
1640 read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); in qcom_nandc_read_cw_raw()
1642 ret = submit_descs(nandc); in qcom_nandc_read_cw_raw()
1643 free_descs(nandc); in qcom_nandc_read_cw_raw()
1645 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1731 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_read_errors() local
1740 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1741 nandc_read_buffer_sync(nandc, true); in parse_read_errors()
1835 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_page_ecc() local
1840 config_nand_page_read(nandc); in read_page_ecc()
1855 if (nandc->props->is_bam) { in read_page_ecc()
1857 nandc_set_read_loc(nandc, 0, 0, data_size, 0); in read_page_ecc()
1858 nandc_set_read_loc(nandc, 1, data_size, in read_page_ecc()
1861 nandc_set_read_loc(nandc, 0, 0, data_size, 1); in read_page_ecc()
1863 nandc_set_read_loc(nandc, 0, data_size, in read_page_ecc()
1868 config_nand_cw_read(nandc, true); in read_page_ecc()
1871 read_data_dma(nandc, FLASH_BUF_ACC, data_buf, in read_page_ecc()
1887 read_data_dma(nandc, FLASH_BUF_ACC + data_size, in read_page_ecc()
1897 ret = submit_descs(nandc); in read_page_ecc()
1898 free_descs(nandc); in read_page_ecc()
1901 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
1915 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in copy_last_cw() local
1920 clear_read_regs(nandc); in copy_last_cw()
1925 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
1930 config_nand_single_cw_page_read(nandc, host->use_ecc); in copy_last_cw()
1932 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
1934 ret = submit_descs(nandc); in copy_last_cw()
1936 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
1938 free_descs(nandc); in copy_last_cw()
1948 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_page() local
1955 clear_bam_transaction(nandc); in qcom_nandc_read_page()
1987 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_oob() local
1990 clear_read_regs(nandc); in qcom_nandc_read_oob()
1991 clear_bam_transaction(nandc); in qcom_nandc_read_oob()
2005 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page() local
2012 clear_read_regs(nandc); in qcom_nandc_write_page()
2013 clear_bam_transaction(nandc); in qcom_nandc_write_page()
2020 config_nand_page_write(nandc); in qcom_nandc_write_page()
2035 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, in qcom_nandc_write_page()
2048 write_data_dma(nandc, FLASH_BUF_ACC + data_size, in qcom_nandc_write_page()
2052 config_nand_cw_write(nandc); in qcom_nandc_write_page()
2058 ret = submit_descs(nandc); in qcom_nandc_write_page()
2060 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2062 free_descs(nandc); in qcom_nandc_write_page()
2077 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page_raw() local
2083 clear_read_regs(nandc); in qcom_nandc_write_page_raw()
2084 clear_bam_transaction(nandc); in qcom_nandc_write_page_raw()
2091 config_nand_page_write(nandc); in qcom_nandc_write_page_raw()
2110 write_data_dma(nandc, reg_off, data_buf, data_size1, in qcom_nandc_write_page_raw()
2115 write_data_dma(nandc, reg_off, oob_buf, oob_size1, in qcom_nandc_write_page_raw()
2120 write_data_dma(nandc, reg_off, data_buf, data_size2, in qcom_nandc_write_page_raw()
2125 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); in qcom_nandc_write_page_raw()
2128 config_nand_cw_write(nandc); in qcom_nandc_write_page_raw()
2131 ret = submit_descs(nandc); in qcom_nandc_write_page_raw()
2133 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2135 free_descs(nandc); in qcom_nandc_write_page_raw()
2154 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_oob() local
2161 clear_bam_transaction(nandc); in qcom_nandc_write_oob()
2167 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2169 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2175 config_nand_page_write(nandc); in qcom_nandc_write_oob()
2176 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_write_oob()
2177 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2178 config_nand_cw_write(nandc); in qcom_nandc_write_oob()
2180 ret = submit_descs(nandc); in qcom_nandc_write_oob()
2182 free_descs(nandc); in qcom_nandc_write_oob()
2185 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2196 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_bad() local
2210 clear_bam_transaction(nandc); in qcom_nandc_block_bad()
2216 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2222 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2225 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2233 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_markbad() local
2237 clear_read_regs(nandc); in qcom_nandc_block_markbad()
2238 clear_bam_transaction(nandc); in qcom_nandc_block_markbad()
2245 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2254 config_nand_page_write(nandc); in qcom_nandc_block_markbad()
2255 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_block_markbad()
2256 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2257 config_nand_cw_write(nandc); in qcom_nandc_block_markbad()
2259 ret = submit_descs(nandc); in qcom_nandc_block_markbad()
2261 free_descs(nandc); in qcom_nandc_block_markbad()
2264 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2280 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_byte() local
2281 u8 *buf = nandc->data_buffer; in qcom_nandc_read_byte()
2292 if (nandc->buf_start < nandc->buf_count) in qcom_nandc_read_byte()
2293 ret = buf[nandc->buf_start++]; in qcom_nandc_read_byte()
2300 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_buf() local
2301 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_read_buf()
2303 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); in qcom_nandc_read_buf()
2304 nandc->buf_start += real_len; in qcom_nandc_read_buf()
2310 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_buf() local
2311 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_write_buf()
2313 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); in qcom_nandc_write_buf()
2315 nandc->buf_start += real_len; in qcom_nandc_write_buf()
2321 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_select_chip() local
2326 dev_warn(nandc->dev, "invalid chip select\n"); in qcom_nandc_select_chip()
2470 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nand_attach_chip() local
2487 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2511 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2558 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2616 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2618 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2621 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2634 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) in qcom_nandc_unalloc() argument
2636 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
2637 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
2638 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
2640 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
2643 if (nandc->tx_chan) in qcom_nandc_unalloc()
2644 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
2646 if (nandc->rx_chan) in qcom_nandc_unalloc()
2647 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
2649 if (nandc->cmd_chan) in qcom_nandc_unalloc()
2650 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
2652 if (nandc->chan) in qcom_nandc_unalloc()
2653 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
2657 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) in qcom_nandc_alloc() argument
2661 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
2663 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
2673 nandc->buf_size = 532; in qcom_nandc_alloc()
2675 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, in qcom_nandc_alloc()
2677 if (!nandc->data_buffer) in qcom_nandc_alloc()
2680 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), in qcom_nandc_alloc()
2682 if (!nandc->regs) in qcom_nandc_alloc()
2685 nandc->reg_read_buf = devm_kcalloc(nandc->dev, in qcom_nandc_alloc()
2686 MAX_REG_RD, sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2688 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
2691 if (nandc->props->is_bam) { in qcom_nandc_alloc()
2692 nandc->reg_read_dma = in qcom_nandc_alloc()
2693 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
2695 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2697 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
2698 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
2702 nandc->tx_chan = dma_request_chan(nandc->dev, "tx"); in qcom_nandc_alloc()
2703 if (IS_ERR(nandc->tx_chan)) { in qcom_nandc_alloc()
2704 ret = PTR_ERR(nandc->tx_chan); in qcom_nandc_alloc()
2705 nandc->tx_chan = NULL; in qcom_nandc_alloc()
2706 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2711 nandc->rx_chan = dma_request_chan(nandc->dev, "rx"); in qcom_nandc_alloc()
2712 if (IS_ERR(nandc->rx_chan)) { in qcom_nandc_alloc()
2713 ret = PTR_ERR(nandc->rx_chan); in qcom_nandc_alloc()
2714 nandc->rx_chan = NULL; in qcom_nandc_alloc()
2715 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2720 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd"); in qcom_nandc_alloc()
2721 if (IS_ERR(nandc->cmd_chan)) { in qcom_nandc_alloc()
2722 ret = PTR_ERR(nandc->cmd_chan); in qcom_nandc_alloc()
2723 nandc->cmd_chan = NULL; in qcom_nandc_alloc()
2724 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2735 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
2736 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
2737 if (!nandc->bam_txn) { in qcom_nandc_alloc()
2738 dev_err(nandc->dev, in qcom_nandc_alloc()
2744 nandc->chan = dma_request_chan(nandc->dev, "rxtx"); in qcom_nandc_alloc()
2745 if (IS_ERR(nandc->chan)) { in qcom_nandc_alloc()
2746 ret = PTR_ERR(nandc->chan); in qcom_nandc_alloc()
2747 nandc->chan = NULL; in qcom_nandc_alloc()
2748 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2754 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
2755 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
2757 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
2758 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
2762 qcom_nandc_unalloc(nandc); in qcom_nandc_alloc()
2767 static int qcom_nandc_setup(struct qcom_nand_controller *nandc) in qcom_nandc_setup() argument
2772 if (!nandc->props->is_qpic) in qcom_nandc_setup()
2773 nandc_write(nandc, SFLASHC_BURST_CFG, 0); in qcom_nandc_setup()
2774 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), in qcom_nandc_setup()
2778 if (nandc->props->is_bam) { in qcom_nandc_setup()
2779 nand_ctrl = nandc_read(nandc, NAND_CTRL); in qcom_nandc_setup()
2789 nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); in qcom_nandc_setup()
2791 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); in qcom_nandc_setup()
2795 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
2796 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
2801 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, in qcom_nand_host_init_and_register() argument
2807 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
2843 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
2854 if (nandc->props->is_bam) { in qcom_nand_host_init_and_register()
2855 free_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2856 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2857 if (!nandc->bam_txn) { in qcom_nand_host_init_and_register()
2858 dev_err(nandc->dev, in qcom_nand_host_init_and_register()
2871 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc) in qcom_probe_nand_devices() argument
2873 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
2885 ret = qcom_nand_host_init_and_register(nandc, host, child); in qcom_probe_nand_devices()
2891 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
2900 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_parse_dt() local
2901 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
2904 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
2906 &nandc->cmd_crci); in qcom_nandc_parse_dt()
2908 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
2913 &nandc->data_crci); in qcom_nandc_parse_dt()
2915 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
2925 struct qcom_nand_controller *nandc; in qcom_nandc_probe() local
2931 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
2932 if (!nandc) in qcom_nandc_probe()
2935 platform_set_drvdata(pdev, nandc); in qcom_nandc_probe()
2936 nandc->dev = dev; in qcom_nandc_probe()
2944 nandc->props = dev_data; in qcom_nandc_probe()
2946 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
2947 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
2948 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
2950 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
2951 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
2952 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
2959 nandc->base = devm_ioremap_resource(dev, res); in qcom_nandc_probe()
2960 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
2961 return PTR_ERR(nandc->base); in qcom_nandc_probe()
2963 nandc->base_phys = res->start; in qcom_nandc_probe()
2964 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
2967 if (!nandc->base_dma) in qcom_nandc_probe()
2970 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
2974 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
2978 ret = qcom_nandc_alloc(nandc); in qcom_nandc_probe()
2982 ret = qcom_nandc_setup(nandc); in qcom_nandc_probe()
2986 ret = qcom_probe_nand_devices(nandc); in qcom_nandc_probe()
2993 qcom_nandc_unalloc(nandc); in qcom_nandc_probe()
2995 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
2997 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
3006 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_remove() local
3012 list_for_each_entry(host, &nandc->host_list, node) { in qcom_nandc_remove()
3019 qcom_nandc_unalloc(nandc); in qcom_nandc_remove()
3021 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
3022 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
3024 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()