Lines Matching +full:supports +full:- +full:cqe
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
167 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
189 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
234 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
243 /* 4C-4F reserved for more max current */
250 /* 55-57 reserved */
255 /* 60-FB reserved */
263 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
293 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
295 /* ADMA2 32-bit DMA descriptor size */
298 /* ADMA2 32-bit descriptor */
307 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
311 * alignment for the descriptor table even in 32-bit DMA mode. Memory
317 * ADMA2 64-bit DMA descriptor size
319 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
321 * register, 128-bit Descriptor will be selected.
323 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
326 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
371 /* Controller has bad caps bits, but really supports DMA */
383 /* Controller can only DMA from 32-bit aligned addresses */
397 /* Controller does not provide transfer-complete interrupt when not busy */
401 /* Controller reports inverted write-protect state */
411 /* Controller cannot do multi-block transfers */
413 /* Controller can only handle 1-bit data transfers */
427 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
431 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
442 /* Controller has a non-standard host control register */
450 /* Controller does not support 64-bit DMA */
454 /* Capability register bit-63 indicates HS400 support */
472 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
473 * for other purposes. Consequently we support 16-bit block count by default.
474 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
509 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
555 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
585 bool cqe_on; /* CQE is operating */
586 u32 cqe_ier; /* CQE interrupt mask */
587 u32 cqe_err_ier; /* CQE error interrupt mask */
592 unsigned int tuning_count; /* Timer count for re-tuning */
593 unsigned int tuning_mode; /* Re-tuning mode supported by host */
594 unsigned int tuning_err; /* Error code for re-tuning */
667 if (unlikely(host->ops->write_l)) in sdhci_writel()
668 host->ops->write_l(host, val, reg); in sdhci_writel()
670 writel(val, host->ioaddr + reg); in sdhci_writel()
675 if (unlikely(host->ops->write_w)) in sdhci_writew()
676 host->ops->write_w(host, val, reg); in sdhci_writew()
678 writew(val, host->ioaddr + reg); in sdhci_writew()
683 if (unlikely(host->ops->write_b)) in sdhci_writeb()
684 host->ops->write_b(host, val, reg); in sdhci_writeb()
686 writeb(val, host->ioaddr + reg); in sdhci_writeb()
691 if (unlikely(host->ops->read_l)) in sdhci_readl()
692 return host->ops->read_l(host, reg); in sdhci_readl()
694 return readl(host->ioaddr + reg); in sdhci_readl()
699 if (unlikely(host->ops->read_w)) in sdhci_readw()
700 return host->ops->read_w(host, reg); in sdhci_readw()
702 return readw(host->ioaddr + reg); in sdhci_readw()
707 if (unlikely(host->ops->read_b)) in sdhci_readb()
708 return host->ops->read_b(host, reg); in sdhci_readb()
710 return readb(host->ioaddr + reg); in sdhci_readb()
717 writel(val, host->ioaddr + reg); in sdhci_writel()
722 writew(val, host->ioaddr + reg); in sdhci_writew()
727 writeb(val, host->ioaddr + reg); in sdhci_writeb()
732 return readl(host->ioaddr + reg); in sdhci_readl()
737 return readw(host->ioaddr + reg); in sdhci_readw()
742 return readb(host->ioaddr + reg); in sdhci_readb()
752 return host->private; in sdhci_priv()