mmc/host/sdhci.h

363 struct sdhci_host {  struct
365 	const char *hw_name;	/* Hardware bus name */
367 	unsigned int quirks;	/* Deviations from spec. */
434 	unsigned int quirks2;	/* More deviations from spec. */
479 	int irq;		/* Device IRQ */
480 	void __iomem *ioaddr;	/* Mapped address */
481 	phys_addr_t mapbase;	/* physical address base */
482 	char *bounce_buffer;	/* For packing SDMA reads/writes */
483 	dma_addr_t bounce_addr;
484 	unsigned int bounce_buffer_size;
486 	const struct sdhci_ops *ops;	/* Low level hw interface */
489 	struct mmc_host *mmc;	/* MMC structure */
490 	struct mmc_host_ops mmc_host_ops;	/* MMC host ops */
491 	u64 dma_mask;		/* custom DMA mask */
494 	struct led_classdev led;	/* LED control */
495 	char led_name[32];
498 	spinlock_t lock;	/* Mutex */
500 	int flags;		/* Host attributes */
515 	unsigned int version;	/* SDHCI spec. version */
517 	unsigned int max_clk;	/* Max possible freq (MHz) */
518 	unsigned int timeout_clk;	/* Timeout freq (KHz) */
519 	unsigned int clk_mul;	/* Clock Muliplier value */
521 	unsigned int clock;	/* Current clock (MHz) */
522 	u8 pwr;			/* Current voltage */
524 	bool runtime_suspended;	/* Host is runtime suspended */
525 	bool bus_on;		/* Bus power prevents runtime suspend */
526 	bool preset_enabled;	/* Preset is enabled */
527 	bool pending_reset;	/* Cmd/data reset is pending */
528 	bool irq_wake_enabled;	/* IRQ wakeup is enabled */
529 	bool v4_mode;		/* Host Version 4 Enable */
530 	bool use_external_dma;	/* Host selects to use external DMA */
531 	bool always_defer_done;	/* Always defer to complete requests */
533 	struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];	/* Requests done */
534 	struct mmc_command *cmd;	/* Current command */
535 	struct mmc_command *data_cmd;	/* Current data command */
536 	struct mmc_command *deferred_cmd;	/* Deferred command */
537 	struct mmc_data *data;	/* Current data request */
538 	unsigned int data_early:1;	/* Data finished before cmd */
540 	struct sg_mapping_iter sg_miter;	/* SG state for PIO */
541 	unsigned int blocks;	/* remaining PIO blocks */
543 	int sg_count;		/* Mapped sg entries */
545 	void *adma_table;	/* ADMA descriptor table */
546 	void *align_buffer;	/* Bounce buffer */
548 	size_t adma_table_sz;	/* ADMA descriptor table size */
549 	size_t align_buffer_sz;	/* Bounce buffer size */
551 	dma_addr_t adma_addr;	/* Mapped ADMA descr. table */
552 	dma_addr_t align_addr;	/* Mapped bounce buffer */
554 	unsigned int desc_sz;	/* ADMA current descriptor size */
555 	unsigned int alloc_desc_sz;	/* ADMA descr. max size host supports */
557 	struct workqueue_struct *complete_wq;	/* Request completion wq */
558 	struct work_struct	complete_work;	/* Request completion work */
560 	struct timer_list timer;	/* Timer for timeouts */
561 	struct timer_list data_timer;	/* Timer for data timeouts */
564 	struct dma_chan *rx_chan;
565 	struct dma_chan *tx_chan;
568 	u32 caps;		/* CAPABILITY_0 */
569 	u32 caps1;		/* CAPABILITY_1 */
570 	bool read_caps;		/* Capability flags have been read */
572 	bool sdhci_core_to_disable_vqmmc;  /* sdhci core can disable vqmmc */
573 	unsigned int            ocr_avail_sdio;	/* OCR bit masks */
574 	unsigned int            ocr_avail_sd;
575 	unsigned int            ocr_avail_mmc;
576 	u32 ocr_mask;		/* available voltages */
578 	unsigned		timing;		/* Current timing */
580 	u32			thread_isr;
583 	u32			ier;
585 	bool			cqe_on;		/* CQE is operating */
586 	u32			cqe_ier;	/* CQE interrupt mask */
587 	u32			cqe_err_ier;	/* CQE error interrupt mask */
589 	wait_queue_head_t	buf_ready_int;	/* Waitqueue for Buffer Read Ready interrupt */
590 	unsigned int		tuning_done;	/* Condition flag set when CMD19 succeeds */
592 	unsigned int		tuning_count;	/* Timer count for re-tuning */
593 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
617 	u32		(*read_l)(struct sdhci_host *host, int reg);  argument