130 	u32 nvquirks;  member
183 	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&  in tegra_sdhci_readw()
228 	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&  in tegra_sdhci_writel()
309 	if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))  in tegra_sdhci_is_pad_and_regulator_valid()
342 	if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)  in tegra_sdhci_set_tap()
350 	if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&  in tegra_sdhci_set_tap()
385 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)  in tegra_sdhci_reset()
388 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)  in tegra_sdhci_reset()
390 		if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)  in tegra_sdhci_reset()
392 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)  in tegra_sdhci_reset()
394 		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)  in tegra_sdhci_reset()
403 	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {  in tegra_sdhci_reset()
641 	if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))  in tegra_sdhci_parse_pad_autocal_dt()
1166 	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)  in tegra_sdhci_voltage_switch()
1216 	if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&  in sdhci_tegra_update_dcmd_desc()
1373 	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1400 	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
1481 	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1519 	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1533 	.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1629 	if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {  in sdhci_tegra_probe()
1637 	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)  in sdhci_tegra_probe()
1651 	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)  in sdhci_tegra_probe()
1681 	if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {  in sdhci_tegra_probe()