Lines Matching +full:disable +full:- +full:wp
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include "sdhci-pci.h"
91 mmc_hostname(host->mmc)); in sdhci_o2_wait_card_detect_stable()
127 mmc_hostname(host->mmc)); in sdhci_o2_enable_internal_clock()
161 pci_read_config_dword(chip->pdev, in o2_pci_set_baseclk()
167 pci_write_config_dword(chip->pdev, in o2_pci_set_baseclk()
211 host->tuning_done = true; in __sdhci_o2_execute_tuning()
215 mmc_hostname(host->mmc)); in __sdhci_o2_execute_tuning()
223 mmc_hostname(host->mmc)); in __sdhci_o2_execute_tuning()
240 struct sdhci_pci_chip *chip = slot->chip; in sdhci_o2_dll_recovery()
243 /* UnLock WP */ in sdhci_o2_dll_recovery()
244 pci_read_config_byte(chip->pdev, in sdhci_o2_dll_recovery()
247 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_o2_dll_recovery()
248 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { in sdhci_o2_dll_recovery()
249 /* Disable clock */ in sdhci_o2_dll_recovery()
257 pci_read_config_dword(chip->pdev, in sdhci_o2_dll_recovery()
262 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); in sdhci_o2_dll_recovery()
263 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); in sdhci_o2_dll_recovery()
269 if (sdhci_o2_get_cd(host->mmc)) { in sdhci_o2_dll_recovery()
282 mmc_hostname(host->mmc), in sdhci_o2_dll_recovery()
283 o2_host->dll_adjust_count); in sdhci_o2_dll_recovery()
287 mmc_hostname(host->mmc)); in sdhci_o2_dll_recovery()
291 o2_host->dll_adjust_count++; in sdhci_o2_dll_recovery()
293 if (!ret && o2_host->dll_adjust_count == DMDN_SZ) in sdhci_o2_dll_recovery()
295 mmc_hostname(host->mmc)); in sdhci_o2_dll_recovery()
296 /* Lock WP */ in sdhci_o2_dll_recovery()
297 pci_read_config_byte(chip->pdev, in sdhci_o2_dll_recovery()
300 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_o2_dll_recovery()
315 if ((host->timing != MMC_TIMING_MMC_HS200) && in sdhci_o2_execute_tuning()
316 (host->timing != MMC_TIMING_UHS_SDR104)) in sdhci_o2_execute_tuning()
321 return -EINVAL; in sdhci_o2_execute_tuning()
332 mmc_hostname(host->mmc)); in sdhci_o2_execute_tuning()
340 mmc_hostname(host->mmc)); in sdhci_o2_execute_tuning()
341 return -EINVAL; in sdhci_o2_execute_tuning()
346 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { in sdhci_o2_execute_tuning()
347 current_bus_width = mmc->ios.bus_width; in sdhci_o2_execute_tuning()
348 mmc->ios.bus_width = MMC_BUS_WIDTH_4; in sdhci_o2_execute_tuning()
361 mmc->ios.bus_width = MMC_BUS_WIDTH_8; in sdhci_o2_execute_tuning()
373 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_o2_execute_tuning()
383 ret = pci_read_config_dword(chip->pdev, in o2_pci_led_enable()
389 pci_write_config_dword(chip->pdev, in o2_pci_led_enable()
392 ret = pci_read_config_dword(chip->pdev, in o2_pci_led_enable()
398 pci_write_config_dword(chip->pdev, in o2_pci_led_enable()
407 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
411 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
414 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
419 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
422 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
426 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
429 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); in sdhci_pci_o2_fujin2_pci_init()
432 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
436 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
439 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
444 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
446 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_fujin2_pci_init()
452 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
455 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_fujin2_pci_init()
461 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
464 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
469 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
472 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
477 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
479 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_fujin2_pci_init()
485 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
493 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); in sdhci_pci_o2_enable_msi()
496 mmc_hostname(host->mmc)); in sdhci_pci_o2_enable_msi()
500 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, in sdhci_pci_o2_enable_msi()
504 mmc_hostname(host->mmc), ret); in sdhci_pci_o2_enable_msi()
508 host->irq = pci_irq_vector(chip->pdev, 0); in sdhci_pci_o2_enable_msi()
518 if (sdhci_o2_get_cd(host->mmc)) { in sdhci_o2_enable_clk()
530 struct sdhci_pci_chip *chip = slot->chip; in sdhci_pci_o2_set_clock()
532 host->mmc->actual_clock = 0; in sdhci_pci_o2_set_clock()
539 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { in sdhci_pci_o2_set_clock()
540 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); in sdhci_pci_o2_set_clock()
543 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_set_clock()
545 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_set_clock()
550 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); in sdhci_pci_o2_set_clock()
553 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_set_clock()
556 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_pci_o2_set_clock()
568 chip = slot->chip; in sdhci_pci_o2_probe_slot()
569 host = slot->host; in sdhci_pci_o2_probe_slot()
571 o2_host->dll_adjust_count = 0; in sdhci_pci_o2_probe_slot()
579 host->mmc->caps |= MMC_CAP_8_BIT_DATA; in sdhci_pci_o2_probe_slot()
581 switch (chip->pdev->device) { in sdhci_pci_o2_probe_slot()
589 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; in sdhci_pci_o2_probe_slot()
593 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { in sdhci_pci_o2_probe_slot()
594 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe_slot()
597 return -EIO; in sdhci_pci_o2_probe_slot()
600 mmc_hostname(host->mmc)); in sdhci_pci_o2_probe_slot()
601 host->flags &= ~SDHCI_SIGNALING_330; in sdhci_pci_o2_probe_slot()
602 host->flags |= SDHCI_SIGNALING_180; in sdhci_pci_o2_probe_slot()
603 host->mmc->caps2 |= MMC_CAP2_NO_SD; in sdhci_pci_o2_probe_slot()
604 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in sdhci_pci_o2_probe_slot()
605 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe_slot()
609 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; in sdhci_pci_o2_probe_slot()
612 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { in sdhci_pci_o2_probe_slot()
613 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; in sdhci_pci_o2_probe_slot()
614 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in sdhci_pci_o2_probe_slot()
615 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_pci_o2_probe_slot()
618 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; in sdhci_pci_o2_probe_slot()
620 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) in sdhci_pci_o2_probe_slot()
641 switch (chip->pdev->device) { in sdhci_pci_o2_probe()
647 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
652 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
655 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); in sdhci_pci_o2_probe()
657 /* Disable CLK_REQ# support after media DET */ in sdhci_pci_o2_probe()
658 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
663 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); in sdhci_pci_o2_probe()
668 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); in sdhci_pci_o2_probe()
672 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); in sdhci_pci_o2_probe()
673 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); in sdhci_pci_o2_probe()
675 /* Disable ADMA1/2 */ in sdhci_pci_o2_probe()
676 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); in sdhci_pci_o2_probe()
677 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); in sdhci_pci_o2_probe()
679 /* Disable the infinite transfer mode */ in sdhci_pci_o2_probe()
680 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
685 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); in sdhci_pci_o2_probe()
687 /* Lock WP */ in sdhci_pci_o2_probe()
688 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
693 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
698 /* UnLock WP */ in sdhci_pci_o2_probe()
699 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
705 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
708 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { in sdhci_pci_o2_probe()
709 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
719 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
725 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
730 pci_write_config_byte(chip->pdev, in sdhci_pci_o2_probe()
741 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
748 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
751 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
756 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); in sdhci_pci_o2_probe()
758 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
765 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
768 /* Disable UHS1 funciton */ in sdhci_pci_o2_probe()
769 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
774 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
777 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) in sdhci_pci_o2_probe()
780 /* Lock WP */ in sdhci_pci_o2_probe()
781 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
786 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
790 /* UnLock WP */ in sdhci_pci_o2_probe()
791 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
797 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
799 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
806 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
812 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
815 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
819 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
824 pci_write_config_byte(chip->pdev, in sdhci_pci_o2_probe()
827 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32); in sdhci_pci_o2_probe()
830 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32); in sdhci_pci_o2_probe()
831 pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1); in sdhci_pci_o2_probe()
832 /* Lock WP */ in sdhci_pci_o2_probe()
833 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
838 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()