60 #define ESDHC_MIX_CTRL			0x48  macro
548 				val = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_readw_le()
566 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_readw_le()
608 			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
616 			writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
619 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
637 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
653 			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
660 			writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writew_le()
801 				new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writeb_le()
803 						host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_writeb_le()
987 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_prepare_tuning()
990 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_prepare_tuning()
1001 	reg = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_post_tuning()
1004 	writel(reg, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_post_tuning()
1048 	m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_hs400_enhanced_strobe()
1053 	writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_hs400_enhanced_strobe()
1148 			ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_reset_tuning()
1151 			writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_reset_tuning()
1184 	m = readl(host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_set_uhs_signaling()
1195 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_set_uhs_signaling()
1200 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_set_uhs_signaling()
1214 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);  in esdhc_set_uhs_signaling()
1602 		writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);  in sdhci_esdhc_imx_probe()