Lines Matching +full:imx7d +full:- +full:usdhc
1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
27 #include <linux/platform_data/mmc-esdhc-imx.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
31 #include "sdhci-esdhc.h"
83 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
134 * open ended multi-blk IO. Otherwise the TC INT wouldn't
144 * The flag tells that the ESDHC controller is an USDHC block that is
156 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
168 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
189 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
299 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
300 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
301 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
302 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
303 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
304 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
305 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
306 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
307 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
308 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
309 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
310 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
311 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
318 return data->socdata == &esdhc_imx25_data; in is_imx25_esdhc()
323 return data->socdata == &esdhc_imx53_data; in is_imx53_esdhc()
328 return data->socdata == &usdhc_imx6q_data; in is_imx6q_usdhc()
333 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); in esdhc_is_usdhc()
338 void __iomem *base = host->ioaddr + (reg & ~0x3); in esdhc_clrset_le()
344 #define DRIVER_NAME "sdhci-esdhc-imx"
346 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
365 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); in esdhc_dump_debug_regs()
377 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, in esdhc_wait_for_card_clock_gate_off()
379 if (ret == -ETIMEDOUT) in esdhc_wait_for_card_clock_gate_off()
380 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); in esdhc_wait_for_card_clock_gate_off()
387 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
393 /* move dat[0-3] bits */ in esdhc_readl_le()
400 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
401 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
419 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
420 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
429 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in esdhc_readl_le()
436 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || in esdhc_readl_le()
437 IS_ERR_OR_NULL(imx_data->pins_200mhz)) in esdhc_readl_le()
460 if ((imx_data->multiblock_status == WAIT_FOR_INT) && in esdhc_readl_le()
463 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le()
465 imx_data->multiblock_status = NO_CMD_PENDING; in esdhc_readl_le()
485 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
487 * re-sample it by the following steps. in esdhc_writel_le()
489 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
491 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
493 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
502 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writel_le()
506 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
508 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
510 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) in esdhc_writel_le()
515 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le()
516 imx_data->multiblock_status = WAIT_FOR_INT; in esdhc_writel_le()
520 writel(val, host->ioaddr + reg); in esdhc_writel_le()
534 * The usdhc register returns a wrong host version. in esdhc_readw_le()
542 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
547 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in esdhc_readw_le()
548 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
549 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) in esdhc_readw_le()
551 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_readw_le()
566 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
574 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_readw_le()
580 return readw(host->ioaddr + reg); in esdhc_readw_le()
591 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
596 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
601 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
606 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
607 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_writew_le()
608 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
616 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
617 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_writew_le()
618 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
619 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
636 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
637 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
641 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writew_le()
642 && (host->cmd->opcode == SD_IO_RW_EXTENDED) in esdhc_writew_le()
643 && (host->cmd->data->blocks > 1) in esdhc_writew_le()
644 && (host->cmd->data->flags & MMC_DATA_READ)) { in esdhc_writew_le()
646 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
648 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
653 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
660 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
666 m = readl(host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
676 * tuning, when send tuning command, usdhc will in esdhc_writew_le()
689 writel(m, host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
695 imx_data->scratchpad = val; in esdhc_writew_le()
699 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) in esdhc_writew_le()
702 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && in esdhc_writew_le()
703 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) in esdhc_writew_le()
704 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; in esdhc_writew_le()
708 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
710 writel(val << 16 | imx_data->scratchpad, in esdhc_writew_le()
711 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
727 val = readl(host->ioaddr + reg); in esdhc_readb_le()
736 return readb(host->ioaddr + reg); in esdhc_readb_le()
776 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writeb_le()
794 * The reset on usdhc fails to clear MIX_CTRL register. in esdhc_writeb_le()
801 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
803 host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
804 imx_data->is_ddr = 0; in esdhc_writeb_le()
822 return pltfm_host->clock; in esdhc_pltfm_get_max_clock()
829 return pltfm_host->clock / 256 / 16; in esdhc_pltfm_get_min_clock()
837 unsigned int host_clock = pltfm_host->clock; in esdhc_pltfm_set_clock()
838 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; in esdhc_pltfm_set_clock()
845 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
847 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
852 host->mmc->actual_clock = 0; in esdhc_pltfm_set_clock()
862 val = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
863 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
864 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
865 writel(val, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
875 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { in esdhc_pltfm_set_clock()
878 max_clock = imx_data->is_ddr ? 45000000 : 150000000; in esdhc_pltfm_set_clock()
890 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
891 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_pltfm_set_clock()
892 clock, host->mmc->actual_clock); in esdhc_pltfm_set_clock()
895 div--; in esdhc_pltfm_set_clock()
904 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, in esdhc_pltfm_set_clock()
906 if (ret == -ETIMEDOUT) in esdhc_pltfm_set_clock()
907 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); in esdhc_pltfm_set_clock()
910 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
912 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
921 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_pltfm_get_ro()
923 switch (boarddata->wp_type) { in esdhc_pltfm_get_ro()
925 return mmc_gpio_get_ro(host->mmc); in esdhc_pltfm_get_ro()
927 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & in esdhc_pltfm_get_ro()
933 return -ENOSYS; in esdhc_pltfm_get_ro()
961 * i.MX uSDHC internally already uses a fixed optimized timing for in usdhc_execute_tuning()
964 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
979 /* IC suggest to reset USDHC before every tuning command */ in esdhc_prepare_tuning()
981 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, in esdhc_prepare_tuning()
983 if (ret == -ETIMEDOUT) in esdhc_prepare_tuning()
984 dev_warn(mmc_dev(host->mmc), in esdhc_prepare_tuning()
987 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
990 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
991 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_prepare_tuning()
992 dev_dbg(mmc_dev(host->mmc), in esdhc_prepare_tuning()
994 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); in esdhc_prepare_tuning()
1001 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1004 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1015 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in esdhc_executing_tuning()
1024 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in esdhc_executing_tuning()
1025 max -= ESDHC_TUNE_CTRL_STEP; in esdhc_executing_tuning()
1034 ret = mmc_send_tuning(host->mmc, opcode, NULL); in esdhc_executing_tuning()
1037 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in esdhc_executing_tuning()
1048 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1049 if (ios->enhanced_strobe) in esdhc_hs400_enhanced_strobe()
1053 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1063 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); in esdhc_change_pinstate()
1065 if (IS_ERR(imx_data->pinctrl) || in esdhc_change_pinstate()
1066 IS_ERR(imx_data->pins_100mhz) || in esdhc_change_pinstate()
1067 IS_ERR(imx_data->pins_200mhz)) in esdhc_change_pinstate()
1068 return -EINVAL; in esdhc_change_pinstate()
1073 pinctrl = imx_data->pins_100mhz; in esdhc_change_pinstate()
1078 pinctrl = imx_data->pins_200mhz; in esdhc_change_pinstate()
1082 return pinctrl_select_default_state(mmc_dev(host->mmc)); in esdhc_change_pinstate()
1085 return pinctrl_select_state(imx_data->pinctrl, pinctrl); in esdhc_change_pinstate()
1106 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & in esdhc_set_strobe_dll()
1108 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_set_strobe_dll()
1113 host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1115 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1119 * for the uSDHC loopback read clock in esdhc_set_strobe_dll()
1121 if (imx_data->boarddata.strobe_dll_delay_target) in esdhc_set_strobe_dll()
1122 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; in esdhc_set_strobe_dll()
1128 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1131 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, in esdhc_set_strobe_dll()
1133 if (ret == -ETIMEDOUT) in esdhc_set_strobe_dll()
1134 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
1147 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_reset_tuning()
1148 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1151 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1152 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_reset_tuning()
1153 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_reset_tuning()
1154 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1157 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1159 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, in esdhc_reset_tuning()
1161 if (ret == -ETIMEDOUT) in esdhc_reset_tuning()
1162 dev_warn(mmc_dev(host->mmc), in esdhc_reset_tuning()
1166 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which in esdhc_reset_tuning()
1169 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1171 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1181 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_set_uhs_signaling()
1184 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1186 imx_data->is_ddr = 0; in esdhc_set_uhs_signaling()
1195 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1200 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1201 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1202 if (boarddata->delay_line) { in esdhc_set_uhs_signaling()
1204 v = boarddata->delay_line << in esdhc_set_uhs_signaling()
1209 writel(v, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_set_uhs_signaling()
1214 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1215 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1217 host->ops->set_clock(host, host->clock); in esdhc_set_uhs_signaling()
1233 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1234 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
1242 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ in esdhc_get_max_timeout_count()
1265 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in esdhc_cqhci_irq()
1302 struct cqhci_host *cq_host = host->mmc->cqe_private; in sdhci_esdhc_imx_hwinit()
1310 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); in sdhci_esdhc_imx_hwinit()
1314 * to zero if this usdhc is chosen to boot system. Change in sdhci_esdhc_imx_hwinit()
1323 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) in sdhci_esdhc_imx_hwinit()
1325 host->ioaddr + SDHCI_HOST_CONTROL); in sdhci_esdhc_imx_hwinit()
1331 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), in sdhci_esdhc_imx_hwinit()
1332 host->ioaddr + 0x6c); in sdhci_esdhc_imx_hwinit()
1335 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); in sdhci_esdhc_imx_hwinit()
1339 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a in sdhci_esdhc_imx_hwinit()
1346 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_hwinit()
1347 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1349 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1351 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; in sdhci_esdhc_imx_hwinit()
1354 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in sdhci_esdhc_imx_hwinit()
1355 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1358 if (imx_data->boarddata.tuning_start_tap) { in sdhci_esdhc_imx_hwinit()
1360 tmp |= imx_data->boarddata.tuning_start_tap; in sdhci_esdhc_imx_hwinit()
1363 if (imx_data->boarddata.tuning_step) { in sdhci_esdhc_imx_hwinit()
1365 tmp |= imx_data->boarddata.tuning_step in sdhci_esdhc_imx_hwinit()
1374 * the buffer read ready interrupt immediately. If usdhc send in sdhci_esdhc_imx_hwinit()
1380 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1381 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in sdhci_esdhc_imx_hwinit()
1387 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1389 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1412 struct cqhci_host *cq_host = mmc->cqe_private; in esdhc_cqe_enable()
1425 if (count-- == 0) { in esdhc_cqe_enable()
1426 dev_warn(mmc_dev(host->mmc), in esdhc_cqe_enable()
1439 if (host->flags & SDHCI_REQ_USE_DMA) in esdhc_cqe_enable()
1441 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) in esdhc_cqe_enable()
1453 dev_err(mmc_dev(host->mmc), in esdhc_cqe_enable()
1477 struct device_node *np = pdev->dev.of_node; in sdhci_esdhc_imx_probe_dt()
1478 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_dt()
1481 if (of_get_property(np, "fsl,wp-controller", NULL)) in sdhci_esdhc_imx_probe_dt()
1482 boarddata->wp_type = ESDHC_WP_CONTROLLER; in sdhci_esdhc_imx_probe_dt()
1489 if (of_property_read_bool(np, "wp-gpios")) in sdhci_esdhc_imx_probe_dt()
1490 boarddata->wp_type = ESDHC_WP_GPIO; in sdhci_esdhc_imx_probe_dt()
1492 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); in sdhci_esdhc_imx_probe_dt()
1493 of_property_read_u32(np, "fsl,tuning-start-tap", in sdhci_esdhc_imx_probe_dt()
1494 &boarddata->tuning_start_tap); in sdhci_esdhc_imx_probe_dt()
1496 of_property_read_u32(np, "fsl,strobe-dll-delay-target", in sdhci_esdhc_imx_probe_dt()
1497 &boarddata->strobe_dll_delay_target); in sdhci_esdhc_imx_probe_dt()
1498 if (of_find_property(np, "no-1-8-v", NULL)) in sdhci_esdhc_imx_probe_dt()
1499 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; in sdhci_esdhc_imx_probe_dt()
1501 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) in sdhci_esdhc_imx_probe_dt()
1502 boarddata->delay_line = 0; in sdhci_esdhc_imx_probe_dt()
1504 mmc_of_parse_voltage(np, &host->ocr_mask); in sdhci_esdhc_imx_probe_dt()
1506 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { in sdhci_esdhc_imx_probe_dt()
1507 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1509 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1514 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_imx_probe_dt()
1518 if (mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_esdhc_imx_probe_dt()
1519 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_dt()
1529 return -ENODEV; in sdhci_esdhc_imx_probe_dt()
1536 of_match_device(imx_esdhc_dt_ids, &pdev->dev); in sdhci_esdhc_imx_probe()
1552 imx_data->socdata = of_id->data; in sdhci_esdhc_imx_probe()
1554 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1555 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_imx_probe()
1557 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdhci_esdhc_imx_probe()
1558 if (IS_ERR(imx_data->clk_ipg)) { in sdhci_esdhc_imx_probe()
1559 err = PTR_ERR(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1563 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdhci_esdhc_imx_probe()
1564 if (IS_ERR(imx_data->clk_ahb)) { in sdhci_esdhc_imx_probe()
1565 err = PTR_ERR(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1569 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); in sdhci_esdhc_imx_probe()
1570 if (IS_ERR(imx_data->clk_per)) { in sdhci_esdhc_imx_probe()
1571 err = PTR_ERR(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1575 pltfm_host->clk = imx_data->clk_per; in sdhci_esdhc_imx_probe()
1576 pltfm_host->clock = clk_get_rate(pltfm_host->clk); in sdhci_esdhc_imx_probe()
1577 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1580 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1583 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1587 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); in sdhci_esdhc_imx_probe()
1588 if (IS_ERR(imx_data->pinctrl)) in sdhci_esdhc_imx_probe()
1589 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); in sdhci_esdhc_imx_probe()
1592 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_esdhc_imx_probe()
1593 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sdhci_esdhc_imx_probe()
1596 host->mmc->caps |= MMC_CAP_CD_WAKE; in sdhci_esdhc_imx_probe()
1598 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) in sdhci_esdhc_imx_probe()
1599 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_esdhc_imx_probe()
1602 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); in sdhci_esdhc_imx_probe()
1603 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in sdhci_esdhc_imx_probe()
1604 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in sdhci_esdhc_imx_probe()
1607 * Link usdhc specific mmc_host_ops execute_tuning function, in sdhci_esdhc_imx_probe()
1610 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; in sdhci_esdhc_imx_probe()
1617 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in sdhci_esdhc_imx_probe()
1621 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) in sdhci_esdhc_imx_probe()
1622 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; in sdhci_esdhc_imx_probe()
1624 if (host->mmc->caps & MMC_CAP_8_BIT_DATA && in sdhci_esdhc_imx_probe()
1625 imx_data->socdata->flags & ESDHC_FLAG_HS400) in sdhci_esdhc_imx_probe()
1626 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; in sdhci_esdhc_imx_probe()
1628 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) in sdhci_esdhc_imx_probe()
1629 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; in sdhci_esdhc_imx_probe()
1631 if (host->mmc->caps & MMC_CAP_8_BIT_DATA && in sdhci_esdhc_imx_probe()
1632 imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { in sdhci_esdhc_imx_probe()
1633 host->mmc->caps2 |= MMC_CAP2_HS400_ES; in sdhci_esdhc_imx_probe()
1634 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_esdhc_imx_probe()
1638 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_probe()
1639 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_esdhc_imx_probe()
1640 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in sdhci_esdhc_imx_probe()
1642 err = -ENOMEM; in sdhci_esdhc_imx_probe()
1646 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; in sdhci_esdhc_imx_probe()
1647 cq_host->ops = &esdhc_cqhci_ops; in sdhci_esdhc_imx_probe()
1649 err = cqhci_init(cq_host, host->mmc, false); in sdhci_esdhc_imx_probe()
1660 pm_runtime_set_active(&pdev->dev); in sdhci_esdhc_imx_probe()
1661 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_esdhc_imx_probe()
1662 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_esdhc_imx_probe()
1663 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_esdhc_imx_probe()
1664 pm_runtime_enable(&pdev->dev); in sdhci_esdhc_imx_probe()
1669 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1671 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1673 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1675 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1676 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_probe()
1688 pm_runtime_get_sync(&pdev->dev); in sdhci_esdhc_imx_remove()
1689 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); in sdhci_esdhc_imx_remove()
1690 pm_runtime_disable(&pdev->dev); in sdhci_esdhc_imx_remove()
1691 pm_runtime_put_noidle(&pdev->dev); in sdhci_esdhc_imx_remove()
1695 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_remove()
1696 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_remove()
1697 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_remove()
1699 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_remove()
1700 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_remove()
1715 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_suspend()
1716 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_suspend()
1721 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && in sdhci_esdhc_suspend()
1722 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { in sdhci_esdhc_suspend()
1723 mmc_retune_timer_stop(host->mmc); in sdhci_esdhc_suspend()
1724 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1727 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_suspend()
1728 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1738 ret = mmc_gpio_set_cd_wake(host->mmc, true); in sdhci_esdhc_suspend()
1752 /* re-initialize hw state in case it's lost in low power mode */ in sdhci_esdhc_resume()
1759 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_resume()
1760 ret = cqhci_resume(host->mmc); in sdhci_esdhc_resume()
1763 ret = mmc_gpio_set_cd_wake(host->mmc, false); in sdhci_esdhc_resume()
1777 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_runtime_suspend()
1778 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_runtime_suspend()
1787 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_runtime_suspend()
1788 mmc_retune_needed(host->mmc); in sdhci_esdhc_runtime_suspend()
1790 imx_data->actual_clock = host->mmc->actual_clock; in sdhci_esdhc_runtime_suspend()
1792 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_suspend()
1793 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_suspend()
1794 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_suspend()
1796 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_suspend()
1797 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_suspend()
1809 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1810 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_runtime_resume()
1812 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) in sdhci_esdhc_runtime_resume()
1813 clk_set_rate(imx_data->clk_per, pltfm_host->clock); in sdhci_esdhc_runtime_resume()
1815 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1819 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1823 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1827 esdhc_pltfm_set_clock(host, imx_data->actual_clock); in sdhci_esdhc_runtime_resume()
1833 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_runtime_resume()
1834 err = cqhci_resume(host->mmc); in sdhci_esdhc_runtime_resume()
1839 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1841 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1843 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1845 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1846 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_resume()
1859 .name = "sdhci-esdhc-imx",