Lines Matching +full:0 +full:x240a
20 #define DW_MMC_240A 0x240a
21 #define DW_MMC_270A 0x270a
23 #define SDMMC_CTRL 0x000
24 #define SDMMC_PWREN 0x004
25 #define SDMMC_CLKDIV 0x008
26 #define SDMMC_CLKSRC 0x00c
27 #define SDMMC_CLKENA 0x010
28 #define SDMMC_TMOUT 0x014
29 #define SDMMC_CTYPE 0x018
30 #define SDMMC_BLKSIZ 0x01c
31 #define SDMMC_BYTCNT 0x020
32 #define SDMMC_INTMASK 0x024
33 #define SDMMC_CMDARG 0x028
34 #define SDMMC_CMD 0x02c
35 #define SDMMC_RESP0 0x030
36 #define SDMMC_RESP1 0x034
37 #define SDMMC_RESP2 0x038
38 #define SDMMC_RESP3 0x03c
39 #define SDMMC_MINTSTS 0x040
40 #define SDMMC_RINTSTS 0x044
41 #define SDMMC_STATUS 0x048
42 #define SDMMC_FIFOTH 0x04c
43 #define SDMMC_CDETECT 0x050
44 #define SDMMC_WRTPRT 0x054
45 #define SDMMC_GPIO 0x058
46 #define SDMMC_TCBCNT 0x05c
47 #define SDMMC_TBBCNT 0x060
48 #define SDMMC_DEBNCE 0x064
49 #define SDMMC_USRID 0x068
50 #define SDMMC_VERID 0x06c
51 #define SDMMC_HCON 0x070
52 #define SDMMC_UHS_REG 0x074
53 #define SDMMC_RST_N 0x078
54 #define SDMMC_BMOD 0x080
55 #define SDMMC_PLDMND 0x084
56 #define SDMMC_DBADDR 0x088
57 #define SDMMC_IDSTS 0x08c
58 #define SDMMC_IDINTEN 0x090
59 #define SDMMC_DSCADDR 0x094
60 #define SDMMC_BUFADDR 0x098
61 #define SDMMC_CDTHRCTL 0x100
66 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
67 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
68 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
69 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
70 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
71 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
72 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
73 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
77 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
78 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
79 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
80 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
81 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
82 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
83 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
84 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
85 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
86 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
87 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
88 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
89 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
90 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
91 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
92 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
97 * Lower than 2.40a : data register offest is 0x100
99 #define DATA_OFFSET 0x100
100 #define DATA_240A_OFFSET 0x200
112 { 0x0000, "CTRL" },
113 { 0x0004, "PWREN" },
114 { 0x0008, "CLKDIV" },
115 { 0x000C, "CLKSRC" },
116 { 0x0010, "CLKENA" },
117 { 0x0014, "TMOUT" },
118 { 0x0018, "CTYPE" },
119 { 0x001C, "BLKSIZ" },
120 { 0x0020, "BYTCNT" },
121 { 0x0024, "INTMASK" },
122 { 0x0028, "CMDARG" },
123 { 0x002C, "CMD" },
124 { 0x0030, "RESP0" },
125 { 0x0034, "RESP1" },
126 { 0x0038, "RESP2" },
127 { 0x003C, "RESP3" },
128 { 0x0040, "MINSTS" },
129 { 0x0044, "RINTSTS" },
130 { 0x0048, "STATUS" },
131 { 0x004C, "FIFOTH" },
132 { 0x0050, "CDETECT" },
133 { 0x0054, "WRTPRT" },
134 { 0x0058, "GPIO" },
135 { 0x005C, "TCBCNT" },
136 { 0x0060, "TBBCNT" },
137 { 0x0064, "DEBNCE" },
138 { 0x0068, "USRID" },
139 { 0x006C, "VERID" },
140 { 0x0070, "HCON" },
141 { 0x0074, "UHS_REG" },
142 { 0x0078, "RST_n" },
143 { 0x0080, "BMOD" },
144 { 0x0084, "PLDMND" },
145 { 0x0088, "DBADDR" },
146 { 0x008C, "IDSTS" },
147 { 0x0090, "IDINTEN" },
148 { 0x0094, "DSCADDR" },
149 { 0x0098, "BUFADDR" },
150 { 0x0100, "CARDTHRCTL" },
151 { 0x0104, "BackEndPwr" },
152 { 0, 0 }
168 #define SDMMC_CTRL_RESET BIT(0)
171 #define SDMMC_CLKEN_ENABLE BIT(0)
174 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
175 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
176 #define SDMMC_TMOUT_RESP_MSK 0xFF
179 #define SDMMC_CTYPE_4BIT BIT(0)
180 #define SDMMC_CTYPE_1BIT 0
199 #define SDMMC_INT_CD BIT(0)
200 #define SDMMC_INT_ERROR 0xbfc2
222 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
224 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
227 #define SDMMC_CMD_FSM_MASK (0x0F << 4)
228 #define SDMMC_CMD_FSM_IDLE (0x00)
232 /* Control SDMMC_UHS_REG defines (base+ 0x74)*/
234 #define SDMMC_UHS_VOLT_REG_18 BIT(0)
237 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
238 ((r) & 0xFFF) << 16 | \
239 ((t) & 0xFFF))
247 #define SDMMC_IDMAC_INT_TI BIT(0)
251 #define SDMMC_IDMAC_SWRESET BIT(0)
253 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
255 #define SDMMC_SET_RD_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
336 #define DW_MMC_CARD_PRESENT 0