Lines Matching +full:supports +full:- +full:cqe

1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/blk-crypto.h>
9 #include <linux/keyslot-manager.h>
12 #include "cqhci-crypto.h"
14 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
30 return mmc->cqe_private; in cqhci_host_from_ksm()
37 u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); in cqhci_crypto_program_key()
40 if (cq_host->ops->program_key) in cqhci_crypto_program_key()
41 return cq_host->ops->program_key(cq_host, cfg, slot); in cqhci_crypto_program_key()
44 cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
48 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]), in cqhci_crypto_program_key()
49 slot_offset + i * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
52 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]), in cqhci_crypto_program_key()
53 slot_offset + 17 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
55 cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]), in cqhci_crypto_program_key()
56 slot_offset + 16 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
67 cq_host->crypto_cap_array; in cqhci_crypto_keyslot_program()
69 &cqhci_crypto_algs[key->crypto_cfg.crypto_mode]; in cqhci_crypto_keyslot_program()
70 u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512; in cqhci_crypto_keyslot_program()
72 int cap_idx = -1; in cqhci_crypto_keyslot_program()
77 for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) { in cqhci_crypto_keyslot_program()
78 if (ccap_array[i].algorithm_id == alg->alg && in cqhci_crypto_keyslot_program()
79 ccap_array[i].key_size == alg->key_size && in cqhci_crypto_keyslot_program()
86 return -EOPNOTSUPP; in cqhci_crypto_keyslot_program()
94 memcpy(cfg.crypto_key, key->raw, key->size/2); in cqhci_crypto_keyslot_program()
96 key->raw + key->size/2, key->size/2); in cqhci_crypto_keyslot_program()
98 memcpy(cfg.crypto_key, key->raw, key->size); in cqhci_crypto_keyslot_program()
131 * controller is runtime-suspended. However, the CQE won't necessarily be
155 * cqhci_crypto_init - initialize CQHCI crypto support
158 * If the driver previously set MMC_CAP2_CRYPTO and the CQE declares
161 * keyslots, and enabling 128-bit task descriptors.
169 struct mmc_host *mmc = cq_host->mmc; in cqhci_crypto_init()
171 struct blk_keyslot_manager *ksm = &mmc->ksm; in cqhci_crypto_init()
178 if (!(mmc->caps2 & MMC_CAP2_CRYPTO) || in cqhci_crypto_init()
182 cq_host->crypto_capabilities.reg_val = in cqhci_crypto_init()
185 cq_host->crypto_cfg_register = in cqhci_crypto_init()
186 (u32)cq_host->crypto_capabilities.config_array_ptr * 0x100; in cqhci_crypto_init()
188 cq_host->crypto_cap_array = in cqhci_crypto_init()
189 devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap, in cqhci_crypto_init()
190 sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL); in cqhci_crypto_init()
191 if (!cq_host->crypto_cap_array) { in cqhci_crypto_init()
192 err = -ENOMEM; in cqhci_crypto_init()
200 num_keyslots = cq_host->crypto_capabilities.config_count + 1; in cqhci_crypto_init()
206 ksm->ksm_ll_ops = cqhci_ksm_ops; in cqhci_crypto_init()
207 ksm->dev = dev; in cqhci_crypto_init()
209 /* Unfortunately, CQHCI crypto only supports 32 DUN bits. */ in cqhci_crypto_init()
210 ksm->max_dun_bytes_supported = 4; in cqhci_crypto_init()
212 ksm->features = BLK_CRYPTO_FEATURE_STANDARD_KEYS; in cqhci_crypto_init()
218 for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap; in cqhci_crypto_init()
220 cq_host->crypto_cap_array[cap_idx].reg_val = in cqhci_crypto_init()
225 cq_host->crypto_cap_array[cap_idx]); in cqhci_crypto_init()
228 ksm->crypto_modes_supported[blk_mode_num] |= in cqhci_crypto_init()
229 cq_host->crypto_cap_array[cap_idx].sdus_mask * 512; in cqhci_crypto_init()
236 /* CQHCI crypto requires the use of 128-bit task descriptors. */ in cqhci_crypto_init()
237 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in cqhci_crypto_init()
242 mmc->caps2 &= ~MMC_CAP2_CRYPTO; in cqhci_crypto_init()