85 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_deactive()  local
88 	scr_reg->CTRL2 |= DEACT;  in rk_scr_deactive()
89 	scr_reg->CTRL1 = 0;  in rk_scr_deactive()
95 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_set_clk()  local
100 	scr_reg->CGSCDIV = ((2 * freq_mhz / 13 - 1)  in rk_scr_set_clk()
102 	DAL_LOGV("scr_reg->CGSCDIV = %d\n", scr_reg->CGSCDIV);  in rk_scr_set_clk()
108 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_set_work_waitingtime()  local
113 	scr_reg->C2CLIM = (wt > 0x0FFFF) ? 0x0FFFF : wt;  in rk_scr_set_work_waitingtime()
119 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_set_etu_duration()  local
125 	scr_reg->CGBITDIV = (scr_reg->CGSCDIV + 1) * (F / D) - 1;  in rk_scr_set_etu_duration()
126 	DAL_LOGV("scr_reg->CGBITDIV = %d\n", scr_reg->CGBITDIV);  in rk_scr_set_etu_duration()
127 	scr_reg->CGBITTUNE = 0;  in rk_scr_set_etu_duration()
135 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_set_scr_voltage()  local
137 	scr_reg->CTRL2 = 0;  in rk_scr_set_scr_voltage()
141 		scr_reg->CTRL2 |= VCC50;  in rk_scr_set_scr_voltage()
145 		scr_reg->CTRL2 |= VCC33;  in rk_scr_set_scr_voltage()
149 		scr_reg->CTRL2 |= VCC18;  in rk_scr_set_scr_voltage()
165 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_set_clockstop_mode()  local
168 		scr_reg->CTRL1 &= ~CLKSTOPVAL;  in rk_scr_set_clockstop_mode()
170 		scr_reg->CTRL1 |= CLKSTOPVAL;  in rk_scr_set_clockstop_mode()
175 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_clock_start()  local
179 	scr_reg->INTEN1 = CLKSTOPRUN;  in rk_scr_clock_start()
181 	scr_reg->CTRL1 &= ~CLKSTOP;  in rk_scr_clock_start()
183 	if (scr_reg->CTRL1 & CLKSTOP)  in rk_scr_clock_start()
188 	while ((scr_reg->CTRL1 & CLKSTOP) && (time_out-- > 0))  in rk_scr_clock_start()
194 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_clock_stop()  local
198 	scr_reg->INTEN1 = CLKSTOPRUN;  in rk_scr_clock_stop()
200 	scr_reg->CTRL1 |= CLKSTOP;  in rk_scr_clock_stop()
203 		while ((!(scr_reg->CTRL1 & CLKSTOP)) && (time_out-- > 0))  in rk_scr_clock_stop()
210 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_reset()  local
219 	scr_reg->INTEN1 = 0;  in rk_scr_reset()
232 		scr_reg->CTRL2 |= WARMRST;  in rk_scr_reset()
236 		scr_reg->CTRL1 = TXEN | RXEN | TS2FIFO | ATRSTFLUSH | GINTEN;  in rk_scr_reset()
237 		scr_reg->CTRL2 |= ACT;  in rk_scr_reset()
245 	scr_reg->RXFIFOTH = MAX_RXTHR;  in rk_scr_reset()
246 	scr_reg->TXFIFOTH = MAX_TXTHR;  in rk_scr_reset()
247 	scr_reg->INTEN1 = RXTHRESHOLD | RXFIFULL | RXPERR |  in rk_scr_reset()
254 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_write_bytes()  local
255 	int	count = FIFO_DEPTH - scr_reg->TXFIFOCNT;  in rk_scr_write_bytes()
263 		scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];  in rk_scr_write_bytes()
268 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_read_bytes()  local
269 	int count = scr_reg->RXFIFOCNT;  in rk_scr_read_bytes()
277 		scr->rx_buf[scr->rx_cnt++] = (unsigned char)scr_reg->FIFODATA;  in rk_scr_read_bytes()
283 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in rk_scr_irqhandler()  local
287 	stat = (unsigned int)scr_reg->INTSTAT1;  in rk_scr_irqhandler()
292 		scr_reg->INTSTAT1 |= TXFIEMPTY;  in rk_scr_irqhandler()
298 			scr_reg->INTEN1 &= ~TXFIEMPTY;  in rk_scr_irqhandler()
299 			scr_reg->INTSTAT1 |= TXFIEMPTY;  in rk_scr_irqhandler()
304 		scr_reg->INTSTAT1 |= CLKSTOPRUN;  in rk_scr_irqhandler()
306 		if (scr_reg->CTRL1 & CLKSTOP)  in rk_scr_irqhandler()
315 		scr_reg->INTEN1 &= ~RXTHRESHOLD;  in rk_scr_irqhandler()
316 		scr_reg->INTSTAT1 |= RXTHRESHOLD | RXFIFULL;  in rk_scr_irqhandler()
327 				scr_reg->INTEN1 &= ~C2CFULL;  in rk_scr_irqhandler()
335 					(unsigned char)scr_reg->FIFODATA;  in rk_scr_irqhandler()
339 		scr_reg->INTEN1 |= RXTHRESHOLD;  in rk_scr_irqhandler()
345 		scr_reg->RXFIFOTH = FIFO_DEPTH;  in rk_scr_irqhandler()
346 		scr_reg->RXFIFOTH = threshold;  in rk_scr_irqhandler()
349 		scr_reg->INTSTAT1 |= ATRDONE;  in rk_scr_irqhandler()
350 		scr_reg->INTEN1 = 0;  in rk_scr_irqhandler()
357 		scr_reg->INTSTAT1 |= ATRFAIL;  in rk_scr_irqhandler()
358 		scr_reg->INTEN1 = 0;  in rk_scr_irqhandler()
365 		scr_reg->INTSTAT1 |= TXPERR;  in rk_scr_irqhandler()
366 		scr_reg->INTEN1 = 0;  in rk_scr_irqhandler()
372 		scr_reg->INTSTAT1 |= RXPERR;  in rk_scr_irqhandler()
373 		scr_reg->INTEN1 = 0;  in rk_scr_irqhandler()
379 		scr_reg->INTSTAT1 |= C2CFULL;  in rk_scr_irqhandler()
380 		scr_reg->INTEN1 = 0;  in rk_scr_irqhandler()
397 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in _rk_scr_init()  local
404 	scr_reg->REPEAT = 0x33;  in _rk_scr_init()
410 	scr_reg->SCGT = 12;  in _rk_scr_init()
416 	scr_reg->C2CLIM = 9600;  in _rk_scr_init()
422 	scr_reg->SCPADS = 0;  in _rk_scr_init()
428 	scr_reg->ADEATIME = 0;  in _rk_scr_init()
435 	scr_reg->LOWRSTTIME = 1000;  in _rk_scr_init()
441 	scr_reg->ATRSTARTLIMIT = 40000;  in _rk_scr_init()
444 	scr_reg->INTEN1 = SCINS;  in _rk_scr_init()
445 	scr_reg->INTEN2 = 0;  in _rk_scr_init()
447 	scr_reg->INTSTAT1 = 0xffff;  in _rk_scr_init()
448 	scr_reg->INTSTAT2 = 0xffff;  in _rk_scr_init()
450 	scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;  in _rk_scr_init()
451 	scr_reg->TXFIFOTH = 0;  in _rk_scr_init()
452 	scr_reg->RXFIFOTH = 0;  in _rk_scr_init()
454 	scr_reg->CTRL1 = 0;  in _rk_scr_init()
455 	scr_reg->CTRL2 = 0;  in _rk_scr_init()
460 	struct scr_reg_t *scr_reg = scr->hw->reg_base;  in _rk_scr_deinit()  local
463 	scr_reg->INTEN1 = 0;  in _rk_scr_deinit()
464 	scr_reg->INTEN2 = 0;  in _rk_scr_deinit()
557 	struct scr_reg_t *scr_reg;  in rk_scr_read()  local
569 	scr_reg = scr->hw->reg_base;  in rk_scr_read()
575 	scr_reg->INTEN1 = 0;  in rk_scr_read()
581 	scr_reg->RXFIFOTH = (scr->rx_expected < MAX_RXTHR)  in rk_scr_read()
585 	scr_reg->INTEN1 = inten1;  in rk_scr_read()
594 	struct scr_reg_t *scr_reg;  in rk_scr_write()  local
611 	scr_reg = scr->hw->reg_base;  in rk_scr_write()
617 	scr_reg->INTEN1 = 0;  in rk_scr_write()
623 	scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;  in rk_scr_write()
628 		if (!(scr_reg->FIFOCTRL & FC_TXFIFULL))  in rk_scr_write()
629 			scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];  in rk_scr_write()
637 	scr_reg->INTEN1 = inten1;  in rk_scr_write()
647 	struct scr_reg_t *scr_reg;  in rk_scr_transfer()  local
666 	scr_reg = scr->hw->reg_base;  in rk_scr_transfer()
672 	scr_reg->INTEN1 = 0;  in rk_scr_transfer()
683 	scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;  in rk_scr_transfer()
685 	scr_reg->RXFIFOTH = (scr->rx_expected < MAX_RXTHR)  in rk_scr_transfer()
687 	scr_reg->TXFIFOTH = MAX_TXTHR;  in rk_scr_transfer()
693 	       !(scr_reg->FIFOCTRL & FC_TXFIFULL)) {  in rk_scr_transfer()
694 		scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];  in rk_scr_transfer()
701 	scr_reg->INTEN1 = inten1;  in rk_scr_transfer()