81 static void rk628_post_process_scaler_init(struct rk628 *rk628,  in rk628_post_process_scaler_init()  argument
126 	dev_info(rk628->dev, "dsp_frame_vst:%d  dsp_frame_hst:%d\n",  in rk628_post_process_scaler_init()
173 	rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0, SW_HRES_MASK,  in rk628_post_process_scaler_init()
175 	rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_VER_DOWN_MODE(ver_down_mode) |  in rk628_post_process_scaler_init()
179 	rk628_i2c_write(rk628, GRF_SCALER_CON1, SCL_V_FACTOR(scl_v_factor) |  in rk628_post_process_scaler_init()
181 	rk628_i2c_write(rk628, GRF_SCALER_CON2, DSP_FRAME_VST(dsp_frame_vst) |  in rk628_post_process_scaler_init()
183 	rk628_i2c_write(rk628, GRF_SCALER_CON3, DSP_HS_END(dsp_hs_end) |  in rk628_post_process_scaler_init()
185 	rk628_i2c_write(rk628, GRF_SCALER_CON4, DSP_HACT_END(dsp_hact_end) |  in rk628_post_process_scaler_init()
187 	rk628_i2c_write(rk628, GRF_SCALER_CON5, DSP_VS_END(dsp_vs_end) |  in rk628_post_process_scaler_init()
189 	rk628_i2c_write(rk628, GRF_SCALER_CON6, DSP_VACT_END(dsp_vact_end) |  in rk628_post_process_scaler_init()
191 	rk628_i2c_write(rk628, GRF_SCALER_CON7, DSP_HBOR_END(dsp_hbor_end) |  in rk628_post_process_scaler_init()
193 	rk628_i2c_write(rk628, GRF_SCALER_CON8, DSP_VBOR_END(dsp_vbor_end) |  in rk628_post_process_scaler_init()
197 void rk628_post_process_init(struct rk628 *rk628)  in rk628_post_process_init()  argument
199 	struct rk628_display_mode *src = &rk628->src_mode;  in rk628_post_process_init()
200 	const struct rk628_display_mode *dst = &rk628->dst_mode;  in rk628_post_process_init()
207 	dev_info(rk628->dev, "src %dx%d clock:%d\n",  in rk628_post_process_init()
210 	dev_info(rk628->dev, "dst %dx%d clock:%llu\n",  in rk628_post_process_init()
213 	rk628_cru_clk_set_rate(rk628, CGU_CLK_RX_READ, src->clock * 1000);  in rk628_post_process_init()
214 	rk628_cru_clk_set_rate(rk628, CGU_SCLK_VOP, dst_rate * 1000);  in rk628_post_process_init()
216 	if (rk628->output_mode == OUTPUT_MODE_HDMI) {  in rk628_post_process_init()
217 		rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_VSYNC_POL_MASK,  in rk628_post_process_init()
218 				      SW_VSYNC_POL(rk628->sync_pol));  in rk628_post_process_init()
219 		rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_HSYNC_POL_MASK,  in rk628_post_process_init()
220 				      SW_HSYNC_POL(rk628->sync_pol));  in rk628_post_process_init()
223 			rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,  in rk628_post_process_init()
226 			rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,  in rk628_post_process_init()
231 	rk628_post_process_scaler_init(rk628, src, dst);  in rk628_post_process_init()
234 static void rk628_post_process_csc(struct rk628 *rk628)  in rk628_post_process_csc()  argument
238 	in_fmt = rk628_get_input_bus_format(rk628);  in rk628_post_process_csc()
239 	out_fmt = rk628_get_output_bus_format(rk628);  in rk628_post_process_csc()
243 			rk628_i2c_write(rk628, GRF_CSC_CTRL_CON,  in rk628_post_process_csc()
248 		rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_R2Y_EN(0));  in rk628_post_process_csc()
249 		rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_Y2R_EN(0));  in rk628_post_process_csc()
254 		rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_R2Y_EN(1));  in rk628_post_process_csc()
256 		rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));  in rk628_post_process_csc()
259 void rk628_post_process_enable(struct rk628 *rk628)  in rk628_post_process_enable()  argument
261 	rk628_post_process_csc(rk628);  in rk628_post_process_enable()
262 	rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_EN(1));  in rk628_post_process_enable()
265 void rk628_post_process_disable(struct rk628 *rk628)  in rk628_post_process_disable()  argument
267 	rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_EN(0));  in rk628_post_process_disable()