Lines Matching +full:4 +full:x
14 #define HDMI_REG_STRIDE 4
15 #define HDMITX_REG(x) ((x * HDMI_REG_STRIDE) + HDMI_BASE) argument
30 #define NOT_RST_ANALOG(x) UPDATE(x, 6, 6) argument
32 #define NOT_RST_DIGITAL(x) UPDATE(x, 5, 5) argument
33 #define REG_CLK_INV_MASK BIT(4)
34 #define REG_CLK_INV(x) UPDATE(x, 4, 4) argument
36 #define VCLK_INV(x) UPDATE(x, 3, 3) argument
38 #define REG_CLK_SOURCE(x) UPDATE(x, 2, 2) argument
40 #define PWR_OFF(x) UPDATE(x, 1, 1) argument
42 #define INT_POL(x) UPDATE(x, 0, 0) argument
50 #define DE_SOURCE(x) UPDATE(x, 0, 0) argument
57 #define VIDEO_INPUT_BITS_MASK GENMASK(5, 4)
58 #define VIDEO_INPUT_12BITS UPDATE(0x0, 5, 4)
59 #define VIDEO_INPUT_10BITS UPDATE(0x1, 5, 4)
60 #define VIDEO_INPUT_REVERT UPDATE(0x2, 5, 4)
61 #define VIDEO_INPUT_8BITS UPDATE(0x3, 5, 4)
63 #define VIDEO_INPUT_CSP(x) UPDATE(x, 0, 0) argument
67 #define VIDEO_AUTO_CSC(x) UPDATE(x, 7, 7) argument
69 #define VIDEO_C0_C2_SWAP(x) UPDATE(x, 0, 0) argument
78 #define COLOR_DEPTH_NOT_INDICATED_MASK BIT(4)
79 #define COLOR_DEPTH_NOT_INDICATED(x) UPDATE(x, 4, 4) argument
81 #define SOF_DISABLE(x) UPDATE(x, 3, 3) argument
83 #define CSC_ENABLE(x) UPDATE(x, 0, 0) argument
87 #define AVMUTE_CLEAR(x) UPDATE(x, 7, 7) argument
89 #define AVMUTE_ENABLE(x) UPDATE(x, 6, 6) argument
91 #define AUDIO_PD(x) UPDATE(x, 2, 2) argument
93 #define AUDIO_MUTE(x) UPDATE(x, 1, 1) argument
95 #define VIDEO_MUTE(x) UPDATE(x, 0, 0) argument
98 #define HSYNC_POLARITY(x) UPDATE(x, 3, 3) argument
99 #define VSYNC_POLARITY(x) UPDATE(x, 2, 2) argument
100 #define INETLACE(x) UPDATE(x, 1, 1) argument
101 #define EXTERANL_VIDEO(x) UPDATE(x, 0, 0) argument
125 #define CTS_SOURCE(x) UPDATE(x, 7, 7) argument
133 #define DOWN_SAMPLE(x) UPDATE(x, 6, 5) argument
140 #define AUDIO_SOURCE(x) UPDATE(x, 4, 3) argument
141 #define MCLK_ENABLE(x) UPDATE(x, 2, 2) argument
150 #define MCLK_RATIO(x) UPDATE(x, 1, 0) argument
171 #define I2S_CHANNEL(x) UPDATE(x, 5, 2) argument
179 #define I2S_MODE(x) UPDATE(x, 1, 0) argument
193 #define AUDIO_STATUS_NLPCM(x) UPDATE(x, 7, 7) argument
218 #define PACKET_GCP_EN(x) UPDATE(x, 7, 7) argument
220 #define PACKET_MSI_EN(x) UPDATE(x, 6, 6) argument
222 #define PACKET_SDI_EN(x) UPDATE(x, 5, 5) argument
223 #define PACKET_VSI_EN_MASK BIT(4)
224 #define PACKET_VSI_EN(x) UPDATE(x, 4, 4) argument
257 #define HDMI_DVI(x) UPDATE(x, 1, 1) argument
269 #define INT_HDCP_OK BIT(4)
274 #define MASK_INT_HOTPLUG(x) UPDATE(x, 5, 5) argument
282 #define TMDS_CLK_SOURCE(x) UPDATE(x, 5, 5) argument
283 #define PHASE_CLK_MASK BIT(4)
284 #define PHASE_CLK(x) UPDATE(x, 4, 4) argument
286 #define TMDS_PHASE_SEL(x) UPDATE(x, 3, 3) argument
288 #define BANDGAP_PWR(x) UPDATE(x, 2, 2) argument
290 #define PLL_PWR_DOWN(x) UPDATE(x, 1, 1) argument
292 #define TMDS_CHG_PWR_DOWN(x) UPDATE(x, 0, 0) argument
295 #define CLK_CHG_PWR(x) UPDATE(x, 3, 3) argument
296 #define DATA_CHG_PWR(x) UPDATE(x, 2, 0) argument
299 #define CLK_MAIN_DRIVER(x) UPDATE(x, 7, 4) argument
300 #define DATA_MAIN_DRIVER(x) UPDATE(x, 3, 0) argument
303 #define PRE_EMPHASIS(x) UPDATE(x, 6, 4) argument
304 #define CLK_PRE_DRIVER(x) UPDATE(x, 3, 2) argument
305 #define DATA_PRE_DRIVER(x) UPDATE(x, 1, 0) argument
308 #define FEEDBACK_DIV_LOW(x) UPDATE(x, 7, 0) argument
310 #define FEEDBACK_DIV_HIGH(x) UPDATE(x, 0, 0) argument
313 #define PRE_DIV_RATIO(x) UPDATE(x, 4, 0) argument
336 #define RX_LA_ERR_MASK BIT(4)