Lines Matching refs:HDMIRX_REG
13 #define HDMIRX_REG(x) ((x) + 0x30000) macro
20 #define HDMI_RX_HDMI_SETUP_CTRL HDMIRX_REG(0x0000)
23 #define HDMI_RX_HDMI_OVR_CTRL HDMIRX_REG(0x0004)
24 #define HDMI_RX_HDMI_TIMER_CTRL HDMIRX_REG(0x0008)
25 #define HDMI_RX_HDMI_RES_OVR HDMIRX_REG(0x0010)
26 #define HDMI_RX_HDMI_RES_STS HDMIRX_REG(0x0014)
27 #define HDMI_RX_HDMI_PLL_CTRL HDMIRX_REG(0x0018)
28 #define HDMI_RX_HDMI_PLL_FRQSET1 HDMIRX_REG(0x001c)
29 #define HDMI_RX_HDMI_PLL_FRQSET2 HDMIRX_REG(0x0020)
30 #define HDMI_RX_HDMI_PLL_PAR1 HDMIRX_REG(0x0024)
31 #define HDMI_RX_HDMI_PLL_PAR2 HDMIRX_REG(0x0028)
32 #define HDMI_RX_HDMI_PLL_PAR3 HDMIRX_REG(0x002c)
33 #define HDMI_RX_HDMI_PLL_LCK_STS HDMIRX_REG(0x0030)
34 #define HDMI_RX_HDMI_CLK_CTRL HDMIRX_REG(0x0034)
35 #define HDMI_RX_HDMI_PCB_CTRL HDMIRX_REG(0x0038)
38 #define HDMI_RX_HDMI_PHS_CTR HDMIRX_REG(0x0040)
39 #define HDMI_RX_HDMI_PHS_USED HDMIRX_REG(0x0044)
40 #define HDMI_RX_HDMI_MISC_CTRL HDMIRX_REG(0x0048)
41 #define HDMI_RX_HDMI_EQOFF_CTRL HDMIRX_REG(0x004c)
42 #define HDMI_RX_HDMI_EQGAIN_CTRL HDMIRX_REG(0x0050)
43 #define HDMI_RX_HDMI_EQCAL_STS HDMIRX_REG(0x0054)
44 #define HDMI_RX_HDMI_EQRESULT HDMIRX_REG(0x0058)
45 #define HDMI_RX_HDMI_EQ_MEAS_CTRL HDMIRX_REG(0x005c)
46 #define HDMI_RX_HDMI_WR_CFG HDMIRX_REG(0x0060)
47 #define HDMI_RX_HDMI_CTRL HDMIRX_REG(0x0064)
48 #define HDMI_RX_HDMI_MODE_RECOVER HDMIRX_REG(0x0080)
67 #define HDMI_RX_HDMI_ERROR_PROTECT HDMIRX_REG(0x0084)
86 #define HDMI_RX_HDMI_ERD_STS HDMIRX_REG(0x0088)
87 #define HDMI_RX_HDMI_SYNC_CTRL HDMIRX_REG(0x0090)
92 #define HDMI_RX_HDMI_CKM_EVLTM HDMIRX_REG(0x0094)
99 #define HDMI_RX_HDMI_CKM_F HDMIRX_REG(0x0098)
104 #define HDMI_RX_HDMI_CKM_RESULT HDMIRX_REG(0x009c)
105 #define HDMI_RX_HDMI_PVO_CONFIG HDMIRX_REG(0x00a0)
106 #define HDMI_RX_HDMI_RESMPL_CTRL HDMIRX_REG(0x00a4)
111 #define HDMI_RX_HDMI_DCM_CTRL HDMIRX_REG(0x00a8)
120 #define HDMI_RX_HDMI_VM_CFG_CH_0_1 HDMIRX_REG(0x00b0)
121 #define HDMI_RX_HDMI_VM_CFG_CH2 HDMIRX_REG(0x00b4)
122 #define HDMI_RX_HDMI_SPARE HDMIRX_REG(0x00b8)
123 #define HDMI_RX_HDMI_STS HDMIRX_REG(0x00bc)
124 #define HDMI_RX_HDCP_CTRL HDMIRX_REG(0x00c0)
139 #define HDMI_RX_HDCP_SETTINGS HDMIRX_REG(0x00c4)
148 #define HDMI_RX_HDCP_SEED HDMIRX_REG(0x00c8)
149 #define HDMI_RX_HDCP_BKSV1 HDMIRX_REG(0x00cc)
150 #define HDMI_RX_HDCP_BKSV0 HDMIRX_REG(0x00d0)
151 #define HDMI_RX_HDCP_KIDX HDMIRX_REG(0x00d4)
152 #define HDMI_RX_HDCP_KEY1 HDMIRX_REG(0x00d8)
153 #define HDMI_RX_HDCP_KEY0 HDMIRX_REG(0x00dc)
154 #define HDMI_RX_HDCP_DBG HDMIRX_REG(0x00e0)
155 #define HDMI_RX_HDCP_AKSV1 HDMIRX_REG(0x00e4)
156 #define HDMI_RX_HDCP_AKSV0 HDMIRX_REG(0x00e8)
157 #define HDMI_RX_HDCP_AN1 HDMIRX_REG(0x00ec)
158 #define HDMI_RX_HDCP_AN0 HDMIRX_REG(0x00f0)
159 #define HDMI_RX_HDCP_EESS_WOO HDMIRX_REG(0x00f4)
160 #define HDMI_RX_HDCP_I2C_TIMEOUT HDMIRX_REG(0x00f8)
161 #define HDMI_RX_HDCP_STS HDMIRX_REG(0x00fc)
162 #define HDMI_RX_MD_HCTRL1 HDMIRX_REG(0x0140)
169 #define HDMI_RX_MD_HCTRL2 HDMIRX_REG(0x0144)
180 #define HDMI_RX_MD_HT0 HDMIRX_REG(0x0148)
181 #define HDMI_RX_MD_HT1 HDMIRX_REG(0x014c)
182 #define HDMI_RX_MD_HACT_PX HDMIRX_REG(0x0150)
183 #define HDMI_RX_MD_HACT_RSV HDMIRX_REG(0x0154)
184 #define HDMI_RX_MD_VCTRL HDMIRX_REG(0x0158)
191 #define HDMI_RX_MD_VSC HDMIRX_REG(0x015c)
192 #define HDMI_RX_MD_VTC HDMIRX_REG(0x0160)
193 #define HDMI_RX_MD_VOL HDMIRX_REG(0x0164)
194 #define HDMI_RX_MD_VAL HDMIRX_REG(0x0168)
195 #define HDMI_RX_MD_VTH HDMIRX_REG(0x016c)
206 #define HDMI_RX_MD_VTL HDMIRX_REG(0x0170)
207 #define HDMI_RX_MD_IL_CTRL HDMIRX_REG(0x0174)
208 #define HDMI_RX_MD_IL_SKEW HDMIRX_REG(0x0178)
209 #define HDMI_RX_MD_IL_POL HDMIRX_REG(0x017c)
214 #define HDMI_RX_MD_STS HDMIRX_REG(0x0180)
216 #define HDMI_RX_AUD_CTRL HDMIRX_REG(0x0200)
217 #define HDMI_RX_AUD_PLL_CTRL HDMIRX_REG(0x0208)
220 #define HDMI_RX_AUD_CLK_CTRL HDMIRX_REG(0x0214)
223 #define HDMI_RX_AUD_CLK_STS HDMIRX_REG(0x023c)
224 #define HDMI_RX_AUD_FIFO_CTRL HDMIRX_REG(0x0240)
230 #define HDMI_RX_AUD_FIFO_TH HDMIRX_REG(0x0244)
237 #define HDMI_RX_AUD_FIFO_FILL_S HDMIRX_REG(0x0248)
238 #define HDMI_RX_AUD_FIFO_CLR_MM HDMIRX_REG(0x024c)
239 #define HDMI_RX_AUD_FIFO_FILLSTS HDMIRX_REG(0x0250)
240 #define HDMI_RX_AUD_CHEXTR_CTRL HDMIRX_REG(0x0254)
242 #define HDMI_RX_AUD_MUTE_CTRL HDMIRX_REG(0x0258)
257 #define HDMI_RX_AUD_FIFO_FILLSTS1 HDMIRX_REG(0x025c)
258 #define HDMI_RX_AUD_SAO_CTRL HDMIRX_REG(0x0260)
263 #define HDMI_RX_AUD_PAO_CTRL HDMIRX_REG(0x0264)
266 #define HDMI_RX_AUD_SPARE HDMIRX_REG(0x0268)
267 #define HDMI_RX_AUD_FIFO_STS HDMIRX_REG(0x027c)
268 #define HDMI_RX_AUDPLL_GEN_CTS HDMIRX_REG(0x0280)
270 #define HDMI_RX_AUDPLL_GEN_N HDMIRX_REG(0x0284)
272 #define HDMI_RX_AUDPLL_GEN_CTRL_RW1 HDMIRX_REG(0x0288)
273 #define HDMI_RX_AUDPLL_GEN_CTRL_RW2 HDMIRX_REG(0x028c)
274 #define HDMI_RX_AUDPLL_GEN_CTRL_W1 HDMIRX_REG(0x0298)
275 #define HDMI_RX_AUDPLL_GEN_STS_RO1 HDMIRX_REG(0x02a0)
276 #define HDMI_RX_AUDPLL_GEN_STS_RO2 HDMIRX_REG(0x02a4)
277 #define HDMI_RX_AUDPLL_SC_NDIVCTSTH HDMIRX_REG(0x02a8)
278 #define HDMI_RX_AUDPLL_SC_CTS HDMIRX_REG(0x02ac)
279 #define HDMI_RX_AUDPLL_SC_N HDMIRX_REG(0x02b0)
280 #define HDMI_RX_AUDPLL_SC_CTRL HDMIRX_REG(0x02b4)
281 #define HDMI_RX_AUDPLL_SC_STS1 HDMIRX_REG(0x02b8)
282 #define HDMI_RX_AUDPLL_SC_STS2 HDMIRX_REG(0x02bc)
283 #define HDMI_RX_SNPS_PHYG3_CTRL HDMIRX_REG(0x02c0)
286 #define HDMI_RX_I2CM_PHYG3_SLAVE HDMIRX_REG(0x02c4)
287 #define HDMI_RX_I2CM_PHYG3_ADDRESS HDMIRX_REG(0x02c8)
288 #define HDMI_RX_I2CM_PHYG3_DATAO HDMIRX_REG(0x02cc)
289 #define HDMI_RX_I2CM_PHYG3_DATAI HDMIRX_REG(0x02d0)
290 #define HDMI_RX_I2CM_PHYG3_OPERATION HDMIRX_REG(0x02d4)
291 #define HDMI_RX_I2CM_PHYG3_MODE HDMIRX_REG(0x02d8)
292 #define HDMI_RX_I2CM_PHYG3_SOFTRST HDMIRX_REG(0x02dc)
293 #define HDMI_RX_I2CM_PHYG3_SS_CNTS HDMIRX_REG(0x02e0)
294 #define HDMI_RX_I2CM_PHYG3_FS_HCNT HDMIRX_REG(0x02e4)
295 #define HDMI_RX_JTAG_CONF HDMIRX_REG(0x02ec)
296 #define HDMI_RX_JTAG_TAP_TCLK HDMIRX_REG(0x02f0)
297 #define HDMI_RX_JTAG_TAP_IN HDMIRX_REG(0x02f4)
298 #define HDMI_RX_JTAG_TAP_OUT HDMIRX_REG(0x02f8)
299 #define HDMI_RX_JTAG_ADDR HDMIRX_REG(0x02fc)
300 #define HDMI_RX_PDEC_CTRL HDMIRX_REG(0x0300)
319 #define HDMI_RX_PDEC_FIFO_CFG HDMIRX_REG(0x0304)
326 #define HDMI_RX_PDEC_FIFO_STS HDMIRX_REG(0x0308)
327 #define HDMI_RX_PDEC_FIFO_DATA HDMIRX_REG(0x030c)
328 #define HDMI_RX_PDEC_AUDIODET_CTRL HDMIRX_REG(0x0310)
331 #define HDMI_RX_PDEC_DBG_ACP HDMIRX_REG(0x031c)
332 #define HDMI_RX_PDEC_DBG_ERR_CORR HDMIRX_REG(0x0320)
333 #define HDMI_RX_PDEC_FIFO_STS1 HDMIRX_REG(0x0324)
334 #define HDMI_RX_PDEC_ACRM_CTRL HDMIRX_REG(0x0330)
337 #define HDMI_RX_PDEC_ACRM_MAX HDMIRX_REG(0x0334)
338 #define HDMI_RX_PDEC_ACRM_MIN HDMIRX_REG(0x0338)
339 #define HDMI_RX_PDEC_ERR_FILTER HDMIRX_REG(0x033c)
340 #define HDMI_RX_PDEC_ASP_CTRL HDMIRX_REG(0x0340)
341 #define HDMI_RX_PDEC_ASP_ERR HDMIRX_REG(0x0344)
342 #define HDMI_RX_PDEC_STS HDMIRX_REG(0x0360)
343 #define HDMI_RX_PDEC_AUD_STS HDMIRX_REG(0x0364)
344 #define HDMI_RX_PDEC_VSI_PAYLOAD0 HDMIRX_REG(0x0368)
345 #define HDMI_RX_PDEC_VSI_PAYLOAD1 HDMIRX_REG(0x036c)
346 #define HDMI_RX_PDEC_VSI_PAYLOAD2 HDMIRX_REG(0x0370)
347 #define HDMI_RX_PDEC_VSI_PAYLOAD3 HDMIRX_REG(0x0374)
348 #define HDMI_RX_PDEC_VSI_PAYLOAD4 HDMIRX_REG(0x0378)
349 #define HDMI_RX_PDEC_VSI_PAYLOAD5 HDMIRX_REG(0x037c)
350 #define HDMI_RX_PDEC_GCP_AVMUTE HDMIRX_REG(0x0380)
352 #define HDMI_RX_PDEC_ACR_CTS HDMIRX_REG(0x0390)
353 #define HDMI_RX_PDEC_ACR_N HDMIRX_REG(0x0394)
354 #define HDMI_RX_PDEC_AVI_HB HDMIRX_REG(0x03a0)
355 #define HDMI_RX_PDEC_AVI_PB HDMIRX_REG(0x03a4)
359 #define HDMI_RX_PDEC_AVI_TBB HDMIRX_REG(0x03a8)
360 #define HDMI_RX_PDEC_AVI_LRB HDMIRX_REG(0x03ac)
361 #define HDMI_RX_PDEC_AIF_CTRL HDMIRX_REG(0x03c0)
363 #define HDMI_RX_PDEC_AIF_HB HDMIRX_REG(0x03c4)
364 #define HDMI_RX_PDEC_AIF_PB0 HDMIRX_REG(0x03c8)
365 #define HDMI_RX_PDEC_AIF_PB1 HDMIRX_REG(0x03cc)
366 #define HDMI_RX_PDEC_GMD_HB HDMIRX_REG(0x03d0)
367 #define HDMI_RX_PDEC_GMD_PB HDMIRX_REG(0x03d4)
368 #define HDMI_RX_PDEC_VSI_ST0 HDMIRX_REG(0x03e0)
369 #define HDMI_RX_PDEC_VSI_ST1 HDMIRX_REG(0x03e4)
370 #define HDMI_RX_PDEC_VSI_PB0 HDMIRX_REG(0x03e8)
371 #define HDMI_RX_PDEC_VSI_PB1 HDMIRX_REG(0x03ec)
372 #define HDMI_RX_PDEC_VSI_PB2 HDMIRX_REG(0x03f0)
373 #define HDMI_RX_PDEC_VSI_PB3 HDMIRX_REG(0x03f4)
374 #define HDMI_RX_PDEC_VSI_PB4 HDMIRX_REG(0x03f8)
375 #define HDMI_RX_PDEC_VSI_PB5 HDMIRX_REG(0x03fc)
376 #define HDMI_RX_CEAVID_CONFIG HDMIRX_REG(0x0400)
377 #define HDMI_RX_CEAVID_3DCONFIG HDMIRX_REG(0x0404)
378 #define HDMI_RX_CEAVID_HCONFIG_LO HDMIRX_REG(0x0408)
379 #define HDMI_RX_CEAVID_HCONFIG_HI HDMIRX_REG(0x040c)
380 #define HDMI_RX_CEAVID_VCONFIG_LO HDMIRX_REG(0x0410)
381 #define HDMI_RX_CEAVID_VCONFIG_HI HDMIRX_REG(0x0414)
382 #define HDMI_RX_CEAVID_STATUS HDMIRX_REG(0x0418)
383 #define HDMI_RX_PDEC_AMP_HB HDMIRX_REG(0x0480)
384 #define HDMI_RX_PDEC_AMP_PAYLOAD0 HDMIRX_REG(0x0484)
385 #define HDMI_RX_PDEC_AMP_PAYLOAD1 HDMIRX_REG(0x0488)
386 #define HDMI_RX_PDEC_AMP_PAYLOAD2 HDMIRX_REG(0x048c)
387 #define HDMI_RX_PDEC_AMP_PAYLOAD3 HDMIRX_REG(0x0490)
388 #define HDMI_RX_PDEC_AMP_PAYLOAD4 HDMIRX_REG(0x0494)
389 #define HDMI_RX_PDEC_AMP_PAYLOAD5 HDMIRX_REG(0x0498)
390 #define HDMI_RX_PDEC_AMP_PAYLOAD6 HDMIRX_REG(0x049c)
391 #define HDMI_RX_PDEC_NTSCVBI_HB HDMIRX_REG(0x04a0)
392 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD0 HDMIRX_REG(0x04a4)
393 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD1 HDMIRX_REG(0x04a8)
394 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD2 HDMIRX_REG(0x04ac)
395 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD3 HDMIRX_REG(0x04b0)
396 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD4 HDMIRX_REG(0x04b4)
397 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD5 HDMIRX_REG(0x04b8)
398 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD6 HDMIRX_REG(0x04bc)
399 #define HDMI_RX_PDEC_DRM_HB HDMIRX_REG(0x04c0)
400 #define HDMI_RX_PDEC_DRM_PAYLOAD0 HDMIRX_REG(0x04c4)
401 #define HDMI_RX_PDEC_DRM_PAYLOAD1 HDMIRX_REG(0x04c8)
402 #define HDMI_RX_PDEC_DRM_PAYLOAD2 HDMIRX_REG(0x04cc)
403 #define HDMI_RX_PDEC_DRM_PAYLOAD3 HDMIRX_REG(0x04d0)
404 #define HDMI_RX_PDEC_DRM_PAYLOAD4 HDMIRX_REG(0x04d4)
405 #define HDMI_RX_PDEC_DRM_PAYLOAD5 HDMIRX_REG(0x04d8)
406 #define HDMI_RX_PDEC_DRM_PAYLOAD6 HDMIRX_REG(0x04dc)
407 #define HDMI_RX_MHLMODE_CTRL HDMIRX_REG(0x0500)
408 #define HDMI_RX_CDSENSE_STATUS HDMIRX_REG(0x0504)
409 #define HDMI_RX_DESERFIFO_CTRL HDMIRX_REG(0x0508)
410 #define HDMI_RX_DESER_INTTRSHCTRL HDMIRX_REG(0x050c)
411 #define HDMI_RX_DESER_INTCNTCTRL HDMIRX_REG(0x0510)
412 #define HDMI_RX_DESER_INTCNT HDMIRX_REG(0x0514)
413 #define HDMI_RX_HDCP_RPT_CTRL HDMIRX_REG(0x0600)
414 #define HDMI_RX_HDCP_RPT_BSTATUS HDMIRX_REG(0x0604)
415 #define HDMI_RX_HDCP_RPT_KSVFIFO_CTRL HDMIRX_REG(0x0608)
416 #define HDMI_RX_HDCP_RPT_KSVFIFO1 HDMIRX_REG(0x060c)
417 #define HDMI_RX_HDCP_RPT_KSVFIFO0 HDMIRX_REG(0x0610)
418 #define HDMI_RX_HDMI20_CONTROL HDMIRX_REG(0x0800)
419 #define HDMI_RX_SCDC_I2CCONFIG HDMIRX_REG(0x0804)
422 #define HDMI_RX_SCDC_CONFIG HDMIRX_REG(0x0808)
423 #define HDMI_RX_CHLOCK_CONFIG HDMIRX_REG(0x080c)
428 #define HDMI_RX_HDCP22_CONTROL HDMIRX_REG(0x081c)
429 #define HDMI_RX_SCDC_REGS0 HDMIRX_REG(0x0820)
430 #define HDMI_RX_SCDC_REGS1 HDMIRX_REG(0x0824)
431 #define HDMI_RX_SCDC_REGS2 HDMIRX_REG(0x0828)
432 #define HDMI_RX_SCDC_REGS3 HDMIRX_REG(0x082c)
433 #define HDMI_RX_SCDC_MANSPEC0 HDMIRX_REG(0x0840)
434 #define HDMI_RX_SCDC_MANSPEC1 HDMIRX_REG(0x0844)
435 #define HDMI_RX_SCDC_MANSPEC2 HDMIRX_REG(0x0848)
436 #define HDMI_RX_SCDC_MANSPEC3 HDMIRX_REG(0x084c)
437 #define HDMI_RX_SCDC_MANSPEC4 HDMIRX_REG(0x0850)
438 #define HDMI_RX_SCDC_WRDATA0 HDMIRX_REG(0x0860)
443 #define HDMI_RX_SCDC_WRDATA1 HDMIRX_REG(0x0864)
444 #define HDMI_RX_SCDC_WRDATA2 HDMIRX_REG(0x0868)
445 #define HDMI_RX_SCDC_WRDATA3 HDMIRX_REG(0x086c)
446 #define HDMI_RX_SCDC_WRDATA4 HDMIRX_REG(0x0870)
447 #define HDMI_RX_SCDC_WRDATA5 HDMIRX_REG(0x0874)
448 #define HDMI_RX_SCDC_WRDATA6 HDMIRX_REG(0x0878)
449 #define HDMI_RX_SCDC_WRDATA7 HDMIRX_REG(0x087c)
450 #define HDMI_RX_HDMI20_STATUS HDMIRX_REG(0x08e0)
451 #define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_IN HDMIRX_REG(0x08e8)
452 #define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_OUT HDMIRX_REG(0x08ec)
453 #define HDMI_RX_HDCP2_ESM_P0_GPIO_IN HDMIRX_REG(0x08f0)
454 #define HDMI_RX_HDCP2_ESM_P0_GPIO_OUT HDMIRX_REG(0x08f4)
455 #define HDMI_RX_HDCP22_STATUS HDMIRX_REG(0x08fc)
456 #define HDMI_RX_HDMI2_IEN_CLR HDMIRX_REG(0x0f60)
457 #define HDMI_RX_HDMI2_IEN_SET HDMIRX_REG(0x0f64)
458 #define HDMI_RX_HDMI2_ISTS HDMIRX_REG(0x0f68)
459 #define HDMI_RX_HDMI2_IEN HDMIRX_REG(0x0f6c)
460 #define HDMI_RX_HDMI2_ICLR HDMIRX_REG(0x0f70)
461 #define HDMI_RX_HDMI2_ISET HDMIRX_REG(0x0f74)
462 #define HDMI_RX_PDEC_IEN_CLR HDMIRX_REG(0x0f78)
463 #define HDMI_RX_PDEC_IEN_SET HDMIRX_REG(0x0f7c)
471 #define HDMI_RX_PDEC_ISTS HDMIRX_REG(0x0f80)
473 #define HDMI_RX_PDEC_IEN HDMIRX_REG(0x0f84)
474 #define HDMI_RX_PDEC_ICLR HDMIRX_REG(0x0f88)
476 #define HDMI_RX_PDEC_ISET HDMIRX_REG(0x0f8c)
477 #define HDMI_RX_AUD_CEC_IEN_CLR HDMIRX_REG(0x0f90)
478 #define HDMI_RX_AUD_CEC_IEN_SET HDMIRX_REG(0x0f94)
479 #define HDMI_RX_AUD_CEC_ISTS HDMIRX_REG(0x0f98)
480 #define HDMI_RX_AUD_CEC_IEN HDMIRX_REG(0x0f9c)
481 #define HDMI_RX_AUD_CEC_ICLR HDMIRX_REG(0x0fa0)
482 #define HDMI_RX_AUD_CEC_ISET HDMIRX_REG(0x0fa4)
483 #define HDMI_RX_AUD_FIFO_IEN_CLR HDMIRX_REG(0x0fa8)
484 #define HDMI_RX_AUD_FIFO_IEN_SET HDMIRX_REG(0x0fac)
485 #define HDMI_RX_AUD_FIFO_ISTS HDMIRX_REG(0x0fb0)
486 #define HDMI_RX_AUD_FIFO_IEN HDMIRX_REG(0x0fb4)
487 #define HDMI_RX_AUD_FIFO_ICLR HDMIRX_REG(0x0fb8)
488 #define HDMI_RX_AUD_FIFO_ISET HDMIRX_REG(0x0fbc)
489 #define HDMI_RX_MD_IEN_CLR HDMIRX_REG(0x0fc0)
490 #define HDMI_RX_MD_IEN_SET HDMIRX_REG(0x0fc4)
497 #define HDMI_RX_MD_ISTS HDMIRX_REG(0x0fc8)
498 #define HDMI_RX_MD_IEN HDMIRX_REG(0x0fcc)
499 #define HDMI_RX_MD_ICLR HDMIRX_REG(0x0fd0)
500 #define HDMI_RX_MD_ISET HDMIRX_REG(0x0fd4)
501 #define HDMI_RX_HDMI_IEN_CLR HDMIRX_REG(0x0fd8)
502 #define HDMI_RX_HDMI_IEN_SET HDMIRX_REG(0x0fdc)
505 #define HDMI_RX_HDMI_ISTS HDMIRX_REG(0x0fe0)
506 #define HDMI_RX_HDMI_IEN HDMIRX_REG(0x0fe4)
507 #define HDMI_RX_HDMI_ICLR HDMIRX_REG(0x0fe8)
508 #define HDMI_RX_HDMI_ISET HDMIRX_REG(0x0fec)
509 #define HDMI_RX_DMI_SW_RST HDMIRX_REG(0x0ff0)
510 #define HDMI_RX_DMI_DISABLE_IF HDMIRX_REG(0x0ff4)
522 #define HDMI_RX_DMI_MODULE_ID_EXT HDMIRX_REG(0x0ff8)
523 #define HDMI_RX_DMI_MODULE_ID HDMIRX_REG(0x0ffc)
524 #define HDMI_RX_CEC_CTRL HDMIRX_REG(0x1f00)
525 #define HDMI_RX_CEC_MASK HDMIRX_REG(0x1f08)
526 #define HDMI_RX_CEC_ADDR_L HDMIRX_REG(0x1f14)
527 #define HDMI_RX_CEC_ADDR_H HDMIRX_REG(0x1f18)
528 #define HDMI_RX_CEC_TX_CNT HDMIRX_REG(0x1f1c)
529 #define HDMI_RX_CEC_RX_CNT HDMIRX_REG(0x1f20)
530 #define HDMI_RX_CEC_TX_DATA_0 HDMIRX_REG(0x1f40)
531 #define HDMI_RX_CEC_TX_DATA_1 HDMIRX_REG(0x1f44)
532 #define HDMI_RX_CEC_TX_DATA_2 HDMIRX_REG(0x1f48)
533 #define HDMI_RX_CEC_TX_DATA_3 HDMIRX_REG(0x1f4c)
534 #define HDMI_RX_CEC_TX_DATA_4 HDMIRX_REG(0x1f50)
535 #define HDMI_RX_CEC_TX_DATA_5 HDMIRX_REG(0x1f54)
536 #define HDMI_RX_CEC_TX_DATA_6 HDMIRX_REG(0x1f58)
537 #define HDMI_RX_CEC_TX_DATA_7 HDMIRX_REG(0x1f5c)
538 #define HDMI_RX_CEC_TX_DATA_8 HDMIRX_REG(0x1f60)
539 #define HDMI_RX_CEC_TX_DATA_9 HDMIRX_REG(0x1f64)
540 #define HDMI_RX_CEC_TX_DATA_10 HDMIRX_REG(0x1f68)
541 #define HDMI_RX_CEC_TX_DATA_11 HDMIRX_REG(0x1f6c)
542 #define HDMI_RX_CEC_TX_DATA_12 HDMIRX_REG(0x1f70)
543 #define HDMI_RX_CEC_TX_DATA_13 HDMIRX_REG(0x1f74)
544 #define HDMI_RX_CEC_TX_DATA_14 HDMIRX_REG(0x1f78)
545 #define HDMI_RX_CEC_TX_DATA_15 HDMIRX_REG(0x1f7c)
546 #define HDMI_RX_CEC_RX_DATA_0 HDMIRX_REG(0x1f80)
547 #define HDMI_RX_CEC_RX_DATA_1 HDMIRX_REG(0x1f84)
548 #define HDMI_RX_CEC_RX_DATA_2 HDMIRX_REG(0x1f88)
549 #define HDMI_RX_CEC_RX_DATA_3 HDMIRX_REG(0x1f8c)
550 #define HDMI_RX_CEC_RX_DATA_4 HDMIRX_REG(0x1f90)
551 #define HDMI_RX_CEC_RX_DATA_5 HDMIRX_REG(0x1f94)
552 #define HDMI_RX_CEC_RX_DATA_6 HDMIRX_REG(0x1f98)
553 #define HDMI_RX_CEC_RX_DATA_7 HDMIRX_REG(0x1f9c)
554 #define HDMI_RX_CEC_RX_DATA_8 HDMIRX_REG(0x1fa0)
555 #define HDMI_RX_CEC_RX_DATA_9 HDMIRX_REG(0x1fa4)
556 #define HDMI_RX_CEC_RX_DATA_10 HDMIRX_REG(0x1fa8)
557 #define HDMI_RX_CEC_RX_DATA_11 HDMIRX_REG(0x1fac)
558 #define HDMI_RX_CEC_RX_DATA_12 HDMIRX_REG(0x1fb0)
559 #define HDMI_RX_CEC_RX_DATA_13 HDMIRX_REG(0x1fb4)
560 #define HDMI_RX_CEC_RX_DATA_14 HDMIRX_REG(0x1fb8)
561 #define HDMI_RX_CEC_RX_DATA_15 HDMIRX_REG(0x1fbc)
562 #define HDMI_RX_CEC_LOCK HDMIRX_REG(0x1fc0)
563 #define HDMI_RX_CEC_WAKEUPCTRL HDMIRX_REG(0x1fc4)
564 #define HDMI_RX_CBUSSWRESETREQ HDMIRX_REG(0x3000)
565 #define HDMI_RX_CBUSENABLEIF HDMIRX_REG(0x3004)
566 #define HDMI_RX_CB_LOCKONCLOCK_STS HDMIRX_REG(0x3010)
567 #define HDMI_RX_CB_LOCKONCLOCKCLR HDMIRX_REG(0x3014)
568 #define HDMI_RX_CBUSIOCTRL HDMIRX_REG(0x3020)
569 #define HDMI_RX_DD_CTRL HDMIRX_REG(0x3040)
570 #define HDMI_RX_DD_OP_CTRL HDMIRX_REG(0x3044)
571 #define HDMI_RX_DD_STS HDMIRX_REG(0x3048)
572 #define HDMI_RX_DD_BYPASS_EN HDMIRX_REG(0x304c)
573 #define HDMI_RX_DD_BYPASS_CTRL HDMIRX_REG(0x3050)
574 #define HDMI_RX_DD_BYPASS_CBUS HDMIRX_REG(0x3054)
575 #define HDMI_RX_LL_TXPCKFIFO HDMIRX_REG(0x3080)
576 #define HDMI_RX_LL_RXPCKFIFO_RD_CLR HDMIRX_REG(0x3084)
577 #define HDMI_RX_LL_RXPCKFIFO_A HDMIRX_REG(0x3088)
578 #define HDMI_RX_LL_RXPCKFIFO_B HDMIRX_REG(0x308c)
579 #define HDMI_RX_LL_TXPCKCTRL_0 HDMIRX_REG(0x3090)
580 #define HDMI_RX_LL_TXPCKCTRL_1 HDMIRX_REG(0x3094)
581 #define HDMI_RX_LL_PCKFIFO_STS HDMIRX_REG(0x309c)
582 #define HDMI_RX_LL_RXPCKCTRL_0 HDMIRX_REG(0x30a0)
583 #define HDMI_RX_LL_RXPCKCTRL_1 HDMIRX_REG(0x30a4)
584 #define HDMI_RX_LL_INTTRSHLDCTRL HDMIRX_REG(0x30b0)
585 #define HDMI_RX_LL_INTCNTCTRL HDMIRX_REG(0x30b4)
586 #define HDMI_RX_LL_INTCNT_0 HDMIRX_REG(0x30b8)
587 #define HDMI_RX_LL_INTCNT_1 HDMIRX_REG(0x30bc)
588 #define HDMI_RX_CBHDCP_OPCTRL HDMIRX_REG(0x3100)
589 #define HDMI_RX_CBHDCP_WDATA_0 HDMIRX_REG(0x3104)
590 #define HDMI_RX_CBHDCP_WDATA_1 HDMIRX_REG(0x3108)
591 #define HDMI_RX_CBHDCP_RDATA_0 HDMIRX_REG(0x310c)
592 #define HDMI_RX_CBHDCP_RDATA_1 HDMIRX_REG(0x3110)
593 #define HDMI_RX_CBHDCP_STATUS HDMIRX_REG(0x3114)
594 #define HDMI_RX_CBHDCP_DDC_REPORT HDMIRX_REG(0x3118)
595 #define HDMI_RX_ISTAT_CB_DD HDMIRX_REG(0x3200)
596 #define HDMI_RX_IMASK_CB_DD HDMIRX_REG(0x3204)
597 #define HDMI_RX_IFORCE_CB_DD HDMIRX_REG(0x3208)
598 #define HDMI_RX_ICLEAR_CB_DD HDMIRX_REG(0x320c)
599 #define HDMI_RX_IMUTE_CB_DD HDMIRX_REG(0x3210)
600 #define HDMI_RX_ISTAT_CB_LL HDMIRX_REG(0x3220)
601 #define HDMI_RX_IMASK_CB_LL HDMIRX_REG(0x3224)
602 #define HDMI_RX_IFORCE_CB_LL HDMIRX_REG(0x3228)
603 #define HDMI_RX_ICLEAR_CB_LL HDMIRX_REG(0x322c)
604 #define HDMI_RX_IMUTE_CB_LL HDMIRX_REG(0x3230)
605 #define HDMI_RX_ISTAT_CB_HDCP HDMIRX_REG(0x3240)
606 #define HDMI_RX_IMASK_CB_HDCP HDMIRX_REG(0x3244)
607 #define HDMI_RX_IFORCE_CB_HDCP HDMIRX_REG(0x3248)
608 #define HDMI_RX_ICLEAR_CB_HDCP HDMIRX_REG(0x324c)
609 #define HDMI_RX_IMUTE_CB_HDCP HDMIRX_REG(0x3250)
610 #define HDMI_RX_ISTAT_CB_MCTRL HDMIRX_REG(0x3260)
611 #define HDMI_RX_IMASK_CB_MCTRL HDMIRX_REG(0x3264)
612 #define HDMI_RX_IFORCE_CB_MCTRL HDMIRX_REG(0x3268)
613 #define HDMI_RX_ICLEAR_CB_MCTRL HDMIRX_REG(0x326c)
614 #define HDMI_RX_IMUTE_CB_MCTRL HDMIRX_REG(0x3270)
615 #define HDMI_RX_IMASTER_MUTE_CB HDMIRX_REG(0x32e0)
616 #define HDMI_RX_IVECTOR_INDEX_CB HDMIRX_REG(0x32e4)