30 int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],  in hl_pci_bars_map()  argument
33 	struct pci_dev *pdev = hdev->pdev;  in hl_pci_bars_map()
38 		dev_err(hdev->dev, "Cannot obtain PCI resources\n");  in hl_pci_bars_map()
44 		hdev->pcie_bar[bar] = is_wc[i] ?  in hl_pci_bars_map()
47 		if (!hdev->pcie_bar[bar]) {  in hl_pci_bars_map()
48 			dev_err(hdev->dev, "pci_ioremap%s_bar failed for %s\n",  in hl_pci_bars_map()
60 		if (hdev->pcie_bar[bar])  in hl_pci_bars_map()
61 			iounmap(hdev->pcie_bar[bar]);  in hl_pci_bars_map()
75 static void hl_pci_bars_unmap(struct hl_device *hdev)  in hl_pci_bars_unmap()  argument
77 	struct pci_dev *pdev = hdev->pdev;  in hl_pci_bars_unmap()
82 		iounmap(hdev->pcie_bar[bar]);  in hl_pci_bars_unmap()
96 static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data)  in hl_pci_elbi_write()  argument
98 	struct pci_dev *pdev = hdev->pdev;  in hl_pci_elbi_write()
103 	if (hdev->pldm)  in hl_pci_elbi_write()
137 		dev_err(hdev->dev, "ELBI write didn't finish in time\n");  in hl_pci_elbi_write()
141 	dev_err(hdev->dev, "ELBI write has undefined bits in status\n");  in hl_pci_elbi_write()
153 int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data)  in hl_pci_iatu_write()  argument
155 	struct asic_fixed_properties *prop = &hdev->asic_prop;  in hl_pci_iatu_write()
164 	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);  in hl_pci_iatu_write()
166 	rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,  in hl_pci_iatu_write()
179 static void hl_pci_reset_link_through_bridge(struct hl_device *hdev)  in hl_pci_reset_link_through_bridge()  argument
181 	struct pci_dev *pdev = hdev->pdev;  in hl_pci_reset_link_through_bridge()
206 int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,  in hl_pci_set_inbound_region()  argument
209 	struct asic_fixed_properties *prop = &hdev->asic_prop;  in hl_pci_set_inbound_region()
218 		bar_phys_base = hdev->pcie_bar_phys[pci_region->bar];  in hl_pci_set_inbound_region()
222 		rc |= hl_pci_iatu_write(hdev, offset + 0x8,  in hl_pci_set_inbound_region()
224 		rc |= hl_pci_iatu_write(hdev, offset + 0xC,  in hl_pci_set_inbound_region()
226 		rc |= hl_pci_iatu_write(hdev, offset + 0x10,  in hl_pci_set_inbound_region()
231 	rc |= hl_pci_iatu_write(hdev, offset + 0x14,  in hl_pci_set_inbound_region()
233 	rc |= hl_pci_iatu_write(hdev, offset + 0x18,  in hl_pci_set_inbound_region()
235 	rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0);  in hl_pci_set_inbound_region()
247 	rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);  in hl_pci_set_inbound_region()
253 	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);  in hl_pci_set_inbound_region()
256 		dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",  in hl_pci_set_inbound_region()
271 int hl_pci_set_outbound_region(struct hl_device *hdev,  in hl_pci_set_outbound_region()  argument
274 	struct asic_fixed_properties *prop = &hdev->asic_prop;  in hl_pci_set_outbound_region()
281 	rc |= hl_pci_iatu_write(hdev, 0x008,  in hl_pci_set_outbound_region()
283 	rc |= hl_pci_iatu_write(hdev, 0x00C,  in hl_pci_set_outbound_region()
285 	rc |= hl_pci_iatu_write(hdev, 0x010,  in hl_pci_set_outbound_region()
287 	rc |= hl_pci_iatu_write(hdev, 0x014, 0);  in hl_pci_set_outbound_region()
289 	if ((hdev->power9_64bit_dma_enable) && (hdev->dma_mask == 64))  in hl_pci_set_outbound_region()
290 		rc |= hl_pci_iatu_write(hdev, 0x018, 0x08000000);  in hl_pci_set_outbound_region()
292 		rc |= hl_pci_iatu_write(hdev, 0x018, 0);  in hl_pci_set_outbound_region()
294 	rc |= hl_pci_iatu_write(hdev, 0x020,  in hl_pci_set_outbound_region()
297 	rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000);  in hl_pci_set_outbound_region()
299 	rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);  in hl_pci_set_outbound_region()
305 	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);  in hl_pci_set_outbound_region()
319 static int hl_pci_set_dma_mask(struct hl_device *hdev)  in hl_pci_set_dma_mask()  argument
321 	struct pci_dev *pdev = hdev->pdev;  in hl_pci_set_dma_mask()
325 	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask));  in hl_pci_set_dma_mask()
327 		dev_err(hdev->dev,  in hl_pci_set_dma_mask()
329 			hdev->dma_mask, rc);  in hl_pci_set_dma_mask()
333 	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask));  in hl_pci_set_dma_mask()
335 		dev_err(hdev->dev,  in hl_pci_set_dma_mask()
337 			hdev->dma_mask, rc);  in hl_pci_set_dma_mask()
356 int hl_pci_init(struct hl_device *hdev, u32 cpu_boot_status_reg,  in hl_pci_init()  argument
359 	struct pci_dev *pdev = hdev->pdev;  in hl_pci_init()
362 	if (hdev->reset_pcilink)  in hl_pci_init()
363 		hl_pci_reset_link_through_bridge(hdev);  in hl_pci_init()
367 		dev_err(hdev->dev, "can't enable PCI device\n");  in hl_pci_init()
373 	rc = hdev->asic_funcs->pci_bars_map(hdev);  in hl_pci_init()
375 		dev_err(hdev->dev, "Failed to initialize PCI BARs\n");  in hl_pci_init()
379 	rc = hdev->asic_funcs->init_iatu(hdev);  in hl_pci_init()
381 		dev_err(hdev->dev, "Failed to initialize iATU\n");  in hl_pci_init()
385 	rc = hl_pci_set_dma_mask(hdev);  in hl_pci_init()
393 	rc = hl_fw_read_preboot_ver(hdev, cpu_boot_status_reg, boot_err0_reg,  in hl_pci_init()
401 	hl_pci_bars_unmap(hdev);  in hl_pci_init()
415 void hl_pci_fini(struct hl_device *hdev)  in hl_pci_fini()  argument
417 	hl_pci_bars_unmap(hdev);  in hl_pci_fini()
419 	pci_clear_master(hdev->pdev);  in hl_pci_fini()
420 	pci_disable_device(hdev->pdev);  in hl_pci_fini()