Lines Matching +full:rcu +full:- +full:endian +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #include <misc/cxl-base.h>
62 /* Configuration and Control area - CAIA 1&2 */
72 /* PSL Lookaside Buffer Management Area - CAIA 1 */
81 /* PSL registers - CAIA 1 */
92 /* PSL registers - CAIA 2 */
114 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
115 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
118 /* Configuration Area - CAIA 1&2 */
125 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
127 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
129 /* Pointer Area - CAIA 1&2 */
133 /* Control Area - CAIA 1&2 */
138 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
141 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
148 /* Configuration and Control Area - CAIA 1&2 */
151 /* Configuration and Control Area - CAIA 1 */
156 /* Configuration and Control Area - CAIA 1 */
158 /* Segment Lookaside Buffer Management - CAIA 1 */
162 /* Interrupt Registers - CAIA 1&2 */
169 /* AFU Registers - CAIA 1&2 */
172 /* Work Element Descriptor - CAIA 1&2 */
182 #define CXL_PSL_Control_tb (0x1ull << (63-63))
183 #define CXL_PSL_Control_Fr (0x1ull << (63-31))
184 #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
185 #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
188 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
189 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
190 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
191 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
197 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
199 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
200 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
201 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
202 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
204 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
205 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
206 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
207 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
209 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
210 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
213 #define CXL_PSL_ID_An_F (1ull << (63-31))
214 #define CXL_PSL_ID_An_L (1ull << (63-30))
217 #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
218 #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
219 #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
220 #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
221 #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
222 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
223 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
224 #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
225 #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
230 #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
231 #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
232 #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
233 #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
234 #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
235 #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
236 #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
237 #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
238 #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
244 #define CXL_PSL_SERR_An_AE (1ull << (63-30))
247 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
249 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
250 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
251 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
252 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
253 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
254 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
256 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
257 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
258 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
260 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
262 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
263 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
264 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
266 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
269 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
270 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
271 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
273 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
275 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
276 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
277 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
279 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
284 #define CXL_SSTP0_An_KS (1ull << (63-2))
285 #define CXL_SSTP0_An_KP (1ull << (63-3))
286 #define CXL_SSTP0_An_N (1ull << (63-4))
287 #define CXL_SSTP0_An_L (1ull << (63-5))
288 #define CXL_SSTP0_An_C (1ull << (63-6))
289 #define CXL_SSTP0_An_TA (1ull << (63-7))
290 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
292 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
294 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
295 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
296 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
297 #define CXL_SSTP1_An_V (1ull << (63-63))
299 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
309 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
312 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
318 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
320 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
321 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
322 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
323 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
324 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
326 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
327 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
328 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
333 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibite…
337 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
338 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
339 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
340 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
341 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
342 #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
358 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
359 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
360 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
361 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
364 #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
366 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
367 #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
368 #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
369 #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
370 #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
371 #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
372 #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */
374 /* cxl_process_element->software_status */
375 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
376 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
377 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
378 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
387 /* SPA->sw_command_status */
412 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
495 /* -1: AFU deconfigured/locked, >= 0: number of readers */
529 irq_hw_number_t offset; member
595 * On bare-metal, pe=external_pe, because we decide what the handle is.
615 struct rcu_head rcu; member
707 * -1: No contexts mapped and new ones cannot be mapped.
722 /* common == phyp + powernv - CAIA 1&2 */
746 /* just powernv - CAIA 1&2 */
768 pdev = to_pci_dev(cxl->dev.parent); in cxl_adapter_link_ok()
777 return cxl->native->p1_mmio + cxl_reg_off(reg); in _cxl_p1_addr()
797 return afu->native->p1n_mmio + cxl_reg_off(reg); in _cxl_p1n_addr()
802 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p1n_write()
808 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p1n_read()
816 return afu->p2n_mmio + cxl_reg_off(reg); in _cxl_p2n_addr()
821 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p2n_write()
827 if (likely(cxl_adapter_link_ok(afu->adapter, afu))) in cxl_p2n_read()
992 * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1092 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1093 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1094 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1095 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1096 int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1097 int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1098 int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1113 * In case an adapter_context_lock is taken the return -EBUSY.
1123 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */