Lines Matching +full:0 +full:xff0000
42 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
43 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
44 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
45 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
46 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
47 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
48 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
49 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
50 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
51 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
52 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
53 { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
54 { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { 0, }
63 PCI_EXP_LNKCTL_ASPMC, 0); in rtsx_pci_disable_aspm()
69 MASK_8_BIT_DEF, (u8) (latency & 0xFF)); in rtsx_comm_set_ltr_latency()
71 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF)); in rtsx_comm_set_ltr_latency()
73 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF)); in rtsx_comm_set_ltr_latency()
75 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF)); in rtsx_comm_set_ltr_latency()
79 return 0; in rtsx_comm_set_ltr_latency()
94 enable ? pcr->aspm_en : 0); in rtsx_comm_set_aspm()
109 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val); in rtsx_set_l1off_sub()
111 return 0; in rtsx_set_l1off_sub()
163 val |= (u32)(addr & 0x3FFF) << 16; in rtsx_pci_write_register()
169 for (i = 0; i < MAX_RW_REG_CNT; i++) { in rtsx_pci_write_register()
171 if ((val & HAIMR_TRANS_END) == 0) { in rtsx_pci_write_register()
174 return 0; in rtsx_pci_write_register()
187 val |= (u32)(addr & 0x3FFF) << 16; in rtsx_pci_read_register()
190 for (i = 0; i < MAX_RW_REG_CNT; i++) { in rtsx_pci_read_register()
192 if ((val & HAIMR_TRANS_END) == 0) in rtsx_pci_read_register()
200 *data = (u8)(val & 0xFF); in rtsx_pci_read_register()
202 return 0; in rtsx_pci_read_register()
208 int err, i, finished = 0; in __rtsx_pci_write_phy_register()
211 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val); in __rtsx_pci_write_phy_register()
212 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8)); in __rtsx_pci_write_phy_register()
213 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); in __rtsx_pci_write_phy_register()
214 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81); in __rtsx_pci_write_phy_register()
216 for (i = 0; i < 100000; i++) { in __rtsx_pci_write_phy_register()
218 if (err < 0) in __rtsx_pci_write_phy_register()
221 if (!(tmp & 0x80)) { in __rtsx_pci_write_phy_register()
230 return 0; in __rtsx_pci_write_phy_register()
244 int err, i, finished = 0; in __rtsx_pci_read_phy_register()
248 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); in __rtsx_pci_read_phy_register()
249 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80); in __rtsx_pci_read_phy_register()
251 for (i = 0; i < 100000; i++) { in __rtsx_pci_read_phy_register()
253 if (err < 0) in __rtsx_pci_read_phy_register()
256 if (!(tmp & 0x80)) { in __rtsx_pci_read_phy_register()
272 return 0; in __rtsx_pci_read_phy_register()
292 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); in rtsx_pci_stop_cmd()
293 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); in rtsx_pci_stop_cmd()
301 u32 val = 0; in rtsx_pci_add_cmd()
304 val |= (u32)(cmd_type & 0x03) << 30; in rtsx_pci_add_cmd()
305 val |= (u32)(reg_addr & 0x3FFF) << 16; in rtsx_pci_add_cmd()
326 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; in rtsx_pci_send_cmd_no_wait()
328 val |= 0x40000000; in rtsx_pci_send_cmd_no_wait()
339 int err = 0; in rtsx_pci_send_cmd()
350 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; in rtsx_pci_send_cmd()
352 val |= 0x40000000; in rtsx_pci_send_cmd()
360 if (timeleft <= 0) { in rtsx_pci_send_cmd()
370 err = 0; in rtsx_pci_send_cmd()
380 if ((err < 0) && (err != -ENODEV)) in rtsx_pci_send_cmd()
397 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); in rtsx_pci_add_sg_tbl()
403 if (len > 0xFFFF) in rtsx_pci_add_sg_tbl()
404 val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16) in rtsx_pci_add_sg_tbl()
418 int err = 0, count; in rtsx_pci_transfer_data()
442 if ((sglist == NULL) || (num_sg <= 0)) in rtsx_pci_dma_map_sg()
467 int i, err = 0; in rtsx_pci_dma_transfer()
477 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; in rtsx_pci_dma_transfer()
478 pcr->sgi = 0; in rtsx_pci_dma_transfer()
497 if (timeleft <= 0) { in rtsx_pci_dma_transfer()
519 if ((err < 0) && (err != -ENODEV)) in rtsx_pci_dma_transfer()
541 for (i = 0; i < buf_len / 256; i++) { in rtsx_pci_read_ppbuf()
544 for (j = 0; j < 256; j++) in rtsx_pci_read_ppbuf()
545 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); in rtsx_pci_read_ppbuf()
548 if (err < 0) in rtsx_pci_read_ppbuf()
558 for (j = 0; j < buf_len % 256; j++) in rtsx_pci_read_ppbuf()
559 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); in rtsx_pci_read_ppbuf()
562 if (err < 0) in rtsx_pci_read_ppbuf()
568 return 0; in rtsx_pci_read_ppbuf()
584 for (i = 0; i < buf_len / 256; i++) { in rtsx_pci_write_ppbuf()
587 for (j = 0; j < 256; j++) { in rtsx_pci_write_ppbuf()
589 reg++, 0xFF, *ptr); in rtsx_pci_write_ppbuf()
594 if (err < 0) in rtsx_pci_write_ppbuf()
601 for (j = 0; j < buf_len % 256; j++) { in rtsx_pci_write_ppbuf()
603 reg++, 0xFF, *ptr); in rtsx_pci_write_ppbuf()
608 if (err < 0) in rtsx_pci_write_ppbuf()
612 return 0; in rtsx_pci_write_ppbuf()
620 while (*tbl & 0xFFFF0000) { in rtsx_pci_set_pull_ctl()
622 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); in rtsx_pci_set_pull_ctl()
672 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier); in rtsx_pci_enable_bus_int()
721 if (err < 0) in rtsx_pci_switch_clock()
741 return 0; in rtsx_pci_switch_clock()
780 0xFF, (div << 4) | mcu_cnt); in rtsx_pci_switch_clock()
781 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rtsx_pci_switch_clock()
784 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in rtsx_pci_switch_clock()
788 PHASE_NOT_RESET, 0); in rtsx_pci_switch_clock()
794 if (err < 0) in rtsx_pci_switch_clock()
799 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rtsx_pci_switch_clock()
800 if (err < 0) in rtsx_pci_switch_clock()
804 return 0; in rtsx_pci_switch_clock()
813 return 0; in rtsx_pci_card_power_on()
822 return 0; in rtsx_pci_card_power_off()
841 return 0; in rtsx_pci_card_exclusive_check()
850 return 0; in rtsx_pci_switch_output_voltage()
890 unsigned int card_detect = 0, card_inserted, card_removed; in rtsx_pci_card_detect()
902 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status); in rtsx_pci_card_detect()
907 pcr->card_inserted = 0; in rtsx_pci_card_detect()
908 pcr->card_removed = 0; in rtsx_pci_card_detect()
913 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n", in rtsx_pci_card_detect()
945 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rtsx_pci_process_ocp()
947 pcr->ocp_stat = 0; in rtsx_pci_process_ocp()
957 return 0; in rtsx_pci_process_ocp_interrupt()
973 if ((int_reg & pcr->bier) == 0) { in rtsx_pci_isr()
977 if (int_reg == 0xFFFFFFFF) { in rtsx_pci_isr()
982 int_reg &= (pcr->bier | 0x7FFFFF); in rtsx_pci_isr()
994 pcr->dma_error_count = 0; in rtsx_pci_isr()
1032 pcr->msi_en ? 0 : IRQF_SHARED, in rtsx_pci_acquire_irq()
1043 return 0; in rtsx_pci_acquire_irq()
1068 rtsx_set_l1off_sub_cfg_d0(pcr, 0); in rtsx_comm_pm_power_saving()
1101 /* Set relink_time to 0 */ in rtsx_base_force_power_down()
1102 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rtsx_base_force_power_down()
1103 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rtsx_base_force_power_down()
1105 RELINK_TIME_MASK, 0); in rtsx_base_force_power_down()
1118 rtsx_pci_writel(pcr, RTSX_BIER, 0); in rtsx_pci_power_off()
1119 pcr->bier = 0; in rtsx_pci_power_off()
1121 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); in rtsx_pci_power_off()
1122 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); in rtsx_pci_power_off()
1137 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); in rtsx_pci_enable_ocp()
1138 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); in rtsx_pci_enable_ocp()
1150 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rtsx_pci_disable_ocp()
1166 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); in rtsx_pci_init_ocp()
1196 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rtsx_pci_clear_ocpstat()
1205 rtsx_pci_read_phy_register(pcr, 0x01, &val); in rtsx_pci_enable_oobs_polling()
1207 rtsx_pci_write_phy_register(pcr, 0x01, val); in rtsx_pci_enable_oobs_polling()
1209 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32); in rtsx_pci_enable_oobs_polling()
1210 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05); in rtsx_pci_enable_oobs_polling()
1211 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83); in rtsx_pci_enable_oobs_polling()
1212 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE); in rtsx_pci_enable_oobs_polling()
1221 rtsx_pci_read_phy_register(pcr, 0x01, &val); in rtsx_pci_disable_oobs_polling()
1223 rtsx_pci_write_phy_register(pcr, 0x01, val); in rtsx_pci_disable_oobs_polling()
1225 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03); in rtsx_pci_disable_oobs_polling()
1226 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00); in rtsx_pci_disable_oobs_polling()
1233 MS_CLK_EN | SD40_CLK_EN, 0); in rtsx_sd_power_off_card3v3()
1234 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rtsx_sd_power_off_card3v3()
1241 return 0; in rtsx_sd_power_off_card3v3()
1247 MS_CLK_EN | SD40_CLK_EN, 0); in rtsx_ms_power_off_card3v3()
1251 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0); in rtsx_ms_power_off_card3v3()
1254 return 0; in rtsx_ms_power_off_card3v3()
1274 RTS5261_MCU_CLOCK_GATING, 0); in rtsx_pci_init_hw()
1276 SSC_POWER_DOWN, 0); in rtsx_pci_init_hw()
1278 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); in rtsx_pci_init_hw()
1280 if (err < 0) in rtsx_pci_init_hw()
1289 if (err < 0) in rtsx_pci_init_hw()
1296 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); in rtsx_pci_init_hw()
1298 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_init_hw()
1300 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); in rtsx_pci_init_hw()
1302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); in rtsx_pci_init_hw()
1305 0xFF, pcr->card_drive_sel); in rtsx_pci_init_hw()
1308 0xFF, SSC_8X_EN | SSC_SEL_4M); in rtsx_pci_init_hw()
1310 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1313 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1316 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); in rtsx_pci_init_hw()
1319 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); in rtsx_pci_init_hw()
1326 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); in rtsx_pci_init_hw()
1328 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 in rtsx_pci_init_hw()
1329 * 1: 2M 0: 400k in rtsx_pci_init_hw()
1331 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); in rtsx_pci_init_hw()
1334 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear in rtsx_pci_init_hw()
1335 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear in rtsx_pci_init_hw()
1337 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); in rtsx_pci_init_hw()
1340 if (err < 0) in rtsx_pci_init_hw()
1363 pci_write_config_byte(pdev, 0x70F, 0x5B); in rtsx_pci_init_hw()
1367 if (err < 0) in rtsx_pci_init_hw()
1379 return 0; in rtsx_pci_init_hw()
1391 case 0x5209: in rtsx_pci_init_chip()
1395 case 0x5229: in rtsx_pci_init_chip()
1399 case 0x5289: in rtsx_pci_init_chip()
1403 case 0x5227: in rtsx_pci_init_chip()
1407 case 0x522A: in rtsx_pci_init_chip()
1411 case 0x5249: in rtsx_pci_init_chip()
1415 case 0x524A: in rtsx_pci_init_chip()
1419 case 0x525A: in rtsx_pci_init_chip()
1423 case 0x5287: in rtsx_pci_init_chip()
1427 case 0x5286: in rtsx_pci_init_chip()
1431 case 0x5260: in rtsx_pci_init_chip()
1435 case 0x5261: in rtsx_pci_init_chip()
1439 case 0x5228: in rtsx_pci_init_chip()
1444 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n", in rtsx_pci_init_chip()
1455 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en); in rtsx_pci_init_chip()
1456 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n", in rtsx_pci_init_chip()
1458 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n", in rtsx_pci_init_chip()
1460 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n", in rtsx_pci_init_chip()
1462 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags); in rtsx_pci_init_chip()
1466 if (err < 0) { in rtsx_pci_init_chip()
1471 return 0; in rtsx_pci_init_chip()
1480 int ret, i, bar = 0; in rtsx_pci_probe()
1488 if (ret < 0) in rtsx_pci_probe()
1514 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); in rtsx_pci_probe()
1515 if (ret >= 0) in rtsx_pci_probe()
1519 if (ret < 0) in rtsx_pci_probe()
1525 if (CHK_PCI_PID(pcr, 0x525A)) in rtsx_pci_probe()
1547 pcr->card_inserted = 0; in rtsx_pci_probe()
1548 pcr->card_removed = 0; in rtsx_pci_probe()
1560 if (ret < 0) in rtsx_pci_probe()
1567 if (ret < 0) in rtsx_pci_probe()
1570 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { in rtsx_pci_probe()
1575 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); in rtsx_pci_probe()
1576 if (ret < 0) in rtsx_pci_probe()
1581 return 0; in rtsx_pci_probe()
1619 rtsx_pci_writel(pcr, RTSX_BIER, 0); in rtsx_pci_remove()
1620 pcr->bier = 0; in rtsx_pci_remove()
1672 return 0; in rtsx_pci_suspend()
1680 int ret = 0; in rtsx_pci_resume()
1689 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_resume()