453 struct clk_mgt {  struct
470 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {  argument
1257 	val = readl(prcmu_base + clk_mgt[clock].offset);  in request_clock()
1259 		val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);  in request_clock()
1261 		clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);  in request_clock()
1264 	writel(val, prcmu_base + clk_mgt[clock].offset);  in request_clock()
1440 	val = readl(prcmu_base + clk_mgt[clock].offset);  in clock_rate()
1443 		if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))  in clock_rate()
1448 	val |= clk_mgt[clock].pllsw;  in clock_rate()
1452 		rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);  in clock_rate()
1454 		rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);  in clock_rate()
1456 		rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);  in clock_rate()
1601 	val = readl(prcmu_base + clk_mgt[clock].offset);  in round_clock_rate()
1602 	src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),  in round_clock_rate()
1603 		clk_mgt[clock].branch);  in round_clock_rate()
1606 		if (clk_mgt[clock].clk38div) {  in round_clock_rate()
1761 	val = readl(prcmu_base + clk_mgt[clock].offset);  in set_clock_rate()
1762 	src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),  in set_clock_rate()
1763 		clk_mgt[clock].branch);  in set_clock_rate()
1766 		if (clk_mgt[clock].clk38div) {  in set_clock_rate()
1789 	writel(val, prcmu_base + clk_mgt[clock].offset);  in set_clock_rate()