227 #define MBOX_BIT BIT  macro
228 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
702 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in db8500_prcmu_set_power_state()
711 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_power_state()
745 		while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in config_wakeups()
750 		writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in config_wakeups()
815 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_arm_opp()
822 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_arm_opp()
922 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_ape_opp()
930 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_ape_opp()
987 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_request_ape_opp_100_voltage()
992 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_request_ape_opp_100_voltage()
1016 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in prcmu_release_usb_wakeup_state()
1022 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in prcmu_release_usb_wakeup_state()
1047 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in request_pll()
1053 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in request_pll()
1099 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))  in db8500_prcmu_set_epod()
1109 	writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_epod()
1196 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))  in request_sysclk()
1202 	writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);  in request_sysclk()
1927 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_esram0_deep_sleep()
1937 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_esram0_deep_sleep()
1949 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotdog()
1955 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotdog()
1967 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotmon()
1976 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotmon()
1989 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in config_hot_period()
1995 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in config_hot_period()
2023 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in prcmu_a9wdog()
2033 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in prcmu_a9wdog()
2106 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_read()
2115 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_read()
2156 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_write_masked()
2165 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_write_masked()
2304 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_modem_reset()
2308 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_modem_reset()
2325 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in ack_dbb_wakeup()
2329 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in ack_dbb_wakeup()
2374 	writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);  in read_mailbox_0()
2387 	writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);  in read_mailbox_1()
2395 	writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);  in read_mailbox_2()
2402 	writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);  in read_mailbox_3()
2429 	writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);  in read_mailbox_4()
2441 	writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);  in read_mailbox_5()
2448 	writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);  in read_mailbox_6()
2454 	writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);  in read_mailbox_7()
2481 		if (bits & MBOX_BIT(n)) {  in prcmu_irq_handler()
2482 			bits -= MBOX_BIT(n);  in prcmu_irq_handler()