97 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)  in asic3_read_register()  function
102 EXPORT_SYMBOL_GPL(asic3_read_register);
110 	val = asic3_read_register(asic, reg);  in asic3_set_register()
131 	edge = asic3_read_register(asic,  in asic3_irq_flip_edge()
153 		status = asic3_read_register(asic,  in asic3_irq_demux()
169 				istat = asic3_read_register(asic,  in asic3_irq_demux()
232 	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);  in asic3_mask_gpio_irq()
245 	regval = asic3_read_register(asic,  in asic3_mask_irq()
269 	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);  in asic3_unmask_gpio_irq()
282 	regval = asic3_read_register(asic,  in asic3_unmask_irq()
308 	level = asic3_read_register(asic,  in asic3_gpio_irq_type()
310 	edge = asic3_read_register(asic,  in asic3_gpio_irq_type()
312 	trigger = asic3_read_register(asic,  in asic3_gpio_irq_type()
458 	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);  in asic3_gpio_direction()
502 	return !!(asic3_read_register(asic,  in asic3_gpio_get()
527 	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);  in asic3_gpio_set()
614 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_enable()
630 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_disable()