18 #define FMC2_BCR(x)			((x) * 0x8 + FMC2_BCR1)  macro
183 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_mux()
197 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_waitcfg()
211 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_sync_trans()
225 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_async_trans()
239 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_cpsize()
253 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_address_hold()
272 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_clk_period()
324 		*reg = FMC2_BCR(cs);  in stm32_fmc2_ebi_get_reg()
487 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);  in stm32_fmc2_ebi_set_trans_type()
510 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);  in stm32_fmc2_ebi_set_buswidth()
542 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);  in stm32_fmc2_ebi_set_cpsize()
555 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);  in stm32_fmc2_ebi_set_bl_setup()
572 	regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_set_address_setup()
936 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs),  in stm32_fmc2_ebi_enable_bank()
942 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);  in stm32_fmc2_ebi_disable_bank()
950 		regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);  in stm32_fmc2_ebi_save_setup()
963 		regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]);  in stm32_fmc2_ebi_set_setup()
993 		regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_nwait_used_by_ctrls()