461 					    unsigned long target_volt)  in exynos5_dmc_align_target_voltage()  argument
465 	if (dmc->curr_volt <= target_volt)  in exynos5_dmc_align_target_voltage()
468 	ret = regulator_set_voltage(dmc->vdd_mif, target_volt,  in exynos5_dmc_align_target_voltage()
469 				    target_volt);  in exynos5_dmc_align_target_voltage()
471 		dmc->curr_volt = target_volt;  in exynos5_dmc_align_target_voltage()
487 					    unsigned long target_volt)  in exynos5_dmc_align_bypass_voltage()  argument
491 	if (dmc->curr_volt >= target_volt)  in exynos5_dmc_align_bypass_voltage()
494 	ret = regulator_set_voltage(dmc->vdd_mif, target_volt,  in exynos5_dmc_align_bypass_voltage()
495 				    target_volt);  in exynos5_dmc_align_bypass_voltage()
497 		dmc->curr_volt = target_volt;  in exynos5_dmc_align_bypass_voltage()
536 					   unsigned long target_volt)  in exynos5_dmc_switch_to_bypass_configuration()  argument
545 	ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);  in exynos5_dmc_switch_to_bypass_configuration()
590 				 unsigned long target_volt)  in exynos5_dmc_change_freq_and_volt()  argument
595 							 target_volt);  in exynos5_dmc_change_freq_and_volt()
632 	ret = exynos5_dmc_align_target_voltage(dmc, target_volt);  in exynos5_dmc_change_freq_and_volt()
660 				     unsigned long *target_volt, u32 flags)  in exynos5_dmc_get_volt_freq()  argument
669 	*target_volt = dev_pm_opp_get_voltage(opp);  in exynos5_dmc_get_volt_freq()
692 	unsigned long target_volt = 0;  in exynos5_dmc_target()  local
695 	ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,  in exynos5_dmc_target()
706 	ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);  in exynos5_dmc_target()
1262 	unsigned long target_volt = 0;  in exynos5_dmc_init_clks()  local
1302 					&target_volt, 0);  in exynos5_dmc_init_clks()
1306 	dmc->curr_volt = target_volt;  in exynos5_dmc_init_clks()