Lines Matching refs:tim1
393 u32 tim1 = 0, val = 0; in get_sdram_tim_1_shdw() local
396 tim1 |= val << T_WTR_SHIFT; in get_sdram_tim_1_shdw()
402 tim1 |= (val - 1) << T_RRD_SHIFT; in get_sdram_tim_1_shdw()
405 tim1 |= val << T_RC_SHIFT; in get_sdram_tim_1_shdw()
408 tim1 |= (val - 1) << T_RAS_SHIFT; in get_sdram_tim_1_shdw()
411 tim1 |= val << T_WR_SHIFT; in get_sdram_tim_1_shdw()
414 tim1 |= val << T_RCD_SHIFT; in get_sdram_tim_1_shdw()
417 tim1 |= val << T_RP_SHIFT; in get_sdram_tim_1_shdw()
419 return tim1; in get_sdram_tim_1_shdw()
426 u32 tim1 = 0, val = 0; in get_sdram_tim_1_shdw_derated() local
429 tim1 = val << T_WTR_SHIFT; in get_sdram_tim_1_shdw_derated()
441 tim1 |= val << T_RRD_SHIFT; in get_sdram_tim_1_shdw_derated()
444 tim1 |= (val - 1) << T_RC_SHIFT; in get_sdram_tim_1_shdw_derated()
448 tim1 |= val << T_RAS_SHIFT; in get_sdram_tim_1_shdw_derated()
451 tim1 |= val << T_WR_SHIFT; in get_sdram_tim_1_shdw_derated()
454 tim1 |= (val - 1) << T_RCD_SHIFT; in get_sdram_tim_1_shdw_derated()
457 tim1 |= (val - 1) << T_RP_SHIFT; in get_sdram_tim_1_shdw_derated()
459 return tim1; in get_sdram_tim_1_shdw_derated()
880 u32 tim1, tim3, ref_ctrl, type; in setup_temperature_sensitive_regs() local
886 tim1 = regs->sdram_tim1_shdw; in setup_temperature_sensitive_regs()
898 tim1 = regs->sdram_tim1_shdw_derated; in setup_temperature_sensitive_regs()
904 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); in setup_temperature_sensitive_regs()