Lines Matching refs:ret
67 int ret; in reg_write() local
69 ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf)); in reg_write()
70 if (ret >= 0 && ret < sizeof(wbuf)) in reg_write()
71 ret = -EIO; in reg_write()
72 return (ret == sizeof(wbuf)) ? 0 : ret; in reg_write()
91 int ret; in reg_read() local
93 ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs)); in reg_read()
94 if (ret >= 0 && ret < ARRAY_SIZE(msgs)) in reg_read()
95 ret = -EIO; in reg_read()
96 return (ret == ARRAY_SIZE(msgs)) ? 0 : ret; in reg_read()
112 int ret; in qm1d1c0042_wakeup() local
117 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_wakeup()
118 if (ret == 0) in qm1d1c0042_wakeup()
119 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_wakeup()
121 if (ret < 0) in qm1d1c0042_wakeup()
124 return ret; in qm1d1c0042_wakeup()
183 int i, ret; in qm1d1c0042_set_params() local
205 ret = reg_write(state, 0x02, val); in qm1d1c0042_set_params()
206 if (ret < 0) in qm1d1c0042_set_params()
207 return ret; in qm1d1c0042_set_params()
213 ret = reg_write(state, 0x06, state->regs[0x06]); in qm1d1c0042_set_params()
214 if (ret < 0) in qm1d1c0042_set_params()
215 return ret; in qm1d1c0042_set_params()
219 ret = reg_write(state, 0x07, state->regs[0x07]); in qm1d1c0042_set_params()
220 if (ret < 0) in qm1d1c0042_set_params()
221 return ret; in qm1d1c0042_set_params()
230 ret = reg_write(state, 0x08, val); in qm1d1c0042_set_params()
231 if (ret < 0) in qm1d1c0042_set_params()
232 return ret; in qm1d1c0042_set_params()
251 ret = reg_write(state, 0x09, state->regs[0x09]); in qm1d1c0042_set_params()
252 if (ret == 0) in qm1d1c0042_set_params()
253 ret = reg_write(state, 0x0a, state->regs[0x0a]); in qm1d1c0042_set_params()
254 if (ret == 0) in qm1d1c0042_set_params()
255 ret = reg_write(state, 0x0b, state->regs[0x0b]); in qm1d1c0042_set_params()
256 if (ret != 0) in qm1d1c0042_set_params()
257 return ret; in qm1d1c0042_set_params()
261 ret = reg_write(state, 0x13, state->regs[0x13]); in qm1d1c0042_set_params()
262 if (ret < 0) in qm1d1c0042_set_params()
263 return ret; in qm1d1c0042_set_params()
269 ret = reg_write(state, 0x0c, val); in qm1d1c0042_set_params()
270 if (ret < 0) in qm1d1c0042_set_params()
271 return ret; in qm1d1c0042_set_params()
274 ret = reg_write(state, 0x0c, val); in qm1d1c0042_set_params()
275 if (ret < 0) in qm1d1c0042_set_params()
276 return ret; in qm1d1c0042_set_params()
287 ret = reg_write(state, 0x08, 0x09); in qm1d1c0042_set_params()
288 if (ret < 0) in qm1d1c0042_set_params()
289 return ret; in qm1d1c0042_set_params()
292 ret = reg_write(state, 0x13, state->regs[0x13]); in qm1d1c0042_set_params()
293 if (ret < 0) in qm1d1c0042_set_params()
294 return ret; in qm1d1c0042_set_params()
302 int ret; in qm1d1c0042_sleep() local
308 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_sleep()
309 if (ret == 0) in qm1d1c0042_sleep()
310 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_sleep()
311 if (ret < 0) in qm1d1c0042_sleep()
314 return ret; in qm1d1c0042_sleep()
321 int i, ret; in qm1d1c0042_init() local
328 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */ in qm1d1c0042_init()
329 if (ret < 0) in qm1d1c0042_init()
333 ret = reg_write(state, 0x01, 0x1c); /* soft reset off */ in qm1d1c0042_init()
334 if (ret < 0) in qm1d1c0042_init()
338 ret = reg_read(state, 0x00, &val); in qm1d1c0042_init()
339 if (ret < 0) in qm1d1c0042_init()
347 ret = -EINVAL; in qm1d1c0042_init()
354 ret = reg_write(state, 0x0c, state->regs[0x0c]); in qm1d1c0042_init()
355 if (ret < 0) in qm1d1c0042_init()
361 ret = reg_write(state, i, state->regs[i]); in qm1d1c0042_init()
362 if (ret < 0) in qm1d1c0042_init()
366 ret = reg_write(state, i, state->regs[i]); in qm1d1c0042_init()
367 if (ret < 0) in qm1d1c0042_init()
371 ret = qm1d1c0042_wakeup(state); in qm1d1c0042_init()
372 if (ret < 0) in qm1d1c0042_init()
375 ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch); in qm1d1c0042_init()
376 if (ret < 0) in qm1d1c0042_init()
379 return ret; in qm1d1c0042_init()
384 return ret; in qm1d1c0042_init()