Lines Matching refs:i_flags
94 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags)) in ivtv_irq_work_handler()
97 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags)) in ivtv_irq_work_handler()
100 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags)) in ivtv_irq_work_handler()
103 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PCM, &itv->i_flags)) in ivtv_irq_work_handler()
329 set_bit(IVTV_F_I_WORK_HANDLER_PCM, &itv->i_flags); in dma_post()
330 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags); in dma_post()
401 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags)) in ivtv_dma_stream_dec_prepare()
407 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags)) in ivtv_dma_stream_dec_prepare()
495 set_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags); in ivtv_dma_enc_start()
496 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags); in ivtv_dma_enc_start()
497 set_bit(IVTV_F_I_PIO, &itv->i_flags); in ivtv_dma_enc_start()
503 set_bit(IVTV_F_I_DMA, &itv->i_flags); in ivtv_dma_enc_start()
523 set_bit(IVTV_F_I_DMA, &itv->i_flags); in ivtv_dma_dec_start()
537 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && itv->cur_dma_stream < 0) in ivtv_irq_dma_read()
540 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) { in ivtv_irq_dma_read()
586 clear_bit(IVTV_F_I_UDMA, &itv->i_flags); in ivtv_irq_dma_read()
587 clear_bit(IVTV_F_I_DMA, &itv->i_flags); in ivtv_irq_dma_read()
629 clear_bit(IVTV_F_I_DMA, &itv->i_flags); in ivtv_irq_enc_dma_complete()
651 clear_bit(IVTV_F_I_PIO, &itv->i_flags); in ivtv_irq_enc_pio_complete()
660 clear_bit(IVTV_F_I_PIO, &itv->i_flags); in ivtv_irq_enc_pio_complete()
692 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && in ivtv_irq_dma_err()
732 if (test_bit(IVTV_F_I_UDMA, &itv->i_flags)) { in ivtv_irq_dma_err()
736 clear_bit(IVTV_F_I_UDMA, &itv->i_flags); in ivtv_irq_dma_err()
737 clear_bit(IVTV_F_I_DMA, &itv->i_flags); in ivtv_irq_dma_err()
793 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) { in ivtv_irq_dec_data_req()
814 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) in ivtv_irq_dec_data_req()
869 clear_bit(IVTV_F_I_VALID_DEC_TIMINGS, &itv->i_flags); in ivtv_irq_vsync()
870 clear_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags); in ivtv_irq_vsync()
873 set_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags); in ivtv_irq_vsync()
875 if (test_bit(IVTV_F_I_EV_VSYNC_ENABLED, &itv->i_flags)) { in ivtv_irq_vsync()
876 set_bit(IVTV_F_I_EV_VSYNC, &itv->i_flags); in ivtv_irq_vsync()
887 test_bit(IVTV_F_I_UPDATE_WSS, &itv->i_flags) || in ivtv_irq_vsync()
888 test_bit(IVTV_F_I_UPDATE_VPS, &itv->i_flags) || in ivtv_irq_vsync()
889 test_bit(IVTV_F_I_UPDATE_CC, &itv->i_flags))) { in ivtv_irq_vsync()
890 set_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags); in ivtv_irq_vsync()
891 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags); in ivtv_irq_vsync()
907 set_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags); in ivtv_irq_vsync()
908 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags); in ivtv_irq_vsync()
996 set_bit(IVTV_F_I_EOS, &itv->i_flags); in ivtv_irq_handler()
1018 if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_DMA, &itv->i_flags)) { in ivtv_irq_handler()
1034 test_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags)) in ivtv_irq_handler()
1038 if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_PIO, &itv->i_flags)) { in ivtv_irq_handler()
1052 if (test_and_clear_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags)) { in ivtv_irq_handler()
1069 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags)) in ivtv_unfinished_dma()
1074 clear_bit(IVTV_F_I_UDMA, &itv->i_flags); in ivtv_unfinished_dma()
1075 clear_bit(IVTV_F_I_DMA, &itv->i_flags); in ivtv_unfinished_dma()