37 } while (0)
93 	if (card->nfeeds == 0)  in dvb_bt8xx_stop_feed()
97 	return 0;  in dvb_bt8xx_stop_feed()
107 	return 0;  in is_pci_slot_eq()
116 	for (card_nr = 0; card_nr < bt878_num; card_nr++)  in dvb_bt8xx_878_match()
124 	static u8 mt352_clock_config [] = { 0x89, 0x38, 0x38 };  in thomson_dtt7579_demod_init()
125 	static u8 mt352_reset [] = { 0x50, 0x80 };  in thomson_dtt7579_demod_init()
126 	static u8 mt352_adc_ctl_1_cfg [] = { 0x8E, 0x40 };  in thomson_dtt7579_demod_init()
127 	static u8 mt352_agc_cfg [] = { 0x67, 0x28, 0x20 };  in thomson_dtt7579_demod_init()
128 	static u8 mt352_gpp_ctl_cfg [] = { 0x8C, 0x33 };  in thomson_dtt7579_demod_init()
129 	static u8 mt352_capt_range_cfg[] = { 0x75, 0x32 };  in thomson_dtt7579_demod_init()
140 	return 0;  in thomson_dtt7579_demod_init()
147 	unsigned char bs = 0;  in thomson_dtt7579_tuner_calc_regs()
148 	unsigned char cp = 0;  in thomson_dtt7579_tuner_calc_regs()
156 		cp = 0xb4;  in thomson_dtt7579_tuner_calc_regs()
158 		cp = 0xbc;  in thomson_dtt7579_tuner_calc_regs()
160 		cp = 0xf4;  in thomson_dtt7579_tuner_calc_regs()
162 	if (c->frequency == 0)  in thomson_dtt7579_tuner_calc_regs()
163 		bs = 0x03;  in thomson_dtt7579_tuner_calc_regs()
165 		bs = 0x02;  in thomson_dtt7579_tuner_calc_regs()
167 		bs = 0x08;  in thomson_dtt7579_tuner_calc_regs()
169 	pllbuf[0] = 0x60;  in thomson_dtt7579_tuner_calc_regs()
171 	pllbuf[2] = div & 0xff;  in thomson_dtt7579_tuner_calc_regs()
179 	.demod_address = 0x0f,
184 	.demod_address = 0x0f,
195 	u32 bandsel[]={0,0x00020000,0x00040000,0x00100800,0x00101000,  in cx24108_tuner_set_params()
196 		0x00102000,0x00104000,0x00108000,0x00110000,  in cx24108_tuner_set_params()
197 		0x00120000,0x00140000};  in cx24108_tuner_set_params()
219 	a=n%32; n/=32; if(a==0) n--;  in cx24108_tuner_set_params()
221 	pll=0xf8000000|  in cx24108_tuner_set_params()
223 	    ((n&0x1ff)<<(5+11))|  in cx24108_tuner_set_params()
224 	    ((a&0x1f)<<11);  in cx24108_tuner_set_params()
231 	cx24110_pll_write(fe,0x500c0000);  in cx24108_tuner_set_params()
232 	cx24110_pll_write(fe,0x83f1f800);  in cx24108_tuner_set_params()
234 	//writereg(client,0x56,0x7f);  in cx24108_tuner_set_params()
236 	return 0;  in cx24108_tuner_set_params()
246 	return 0;  in pinnsat_tuner_init()
253 	bttv_write_gpio(card->bttv_nr, 1, 0);   /* relay off */  in pinnsat_tuner_sleep()
255 	return 0;  in pinnsat_tuner_sleep()
259 	.demod_address = 0x55,
269 	struct i2c_msg msg = { .addr = 0x60, .flags = 0, .buf = data, .len = sizeof(data) };  in microtune_mt7202dtf_tuner_set_params()
272 	cfg = 0x88;  in microtune_mt7202dtf_tuner_set_params()
286 		band_select = 0x0e;  in microtune_mt7202dtf_tuner_set_params()
288 		band_select = 0x05;  in microtune_mt7202dtf_tuner_set_params()
290 		band_select = 0x03;  in microtune_mt7202dtf_tuner_set_params()
292 	data[0] = (div >> 8) & 0x7f;  in microtune_mt7202dtf_tuner_set_params()
293 	data[1] = div & 0xff;  in microtune_mt7202dtf_tuner_set_params()
294 	data[2] = ((div >> 10) & 0x60) | cfg;  in microtune_mt7202dtf_tuner_set_params()
311 	.demod_address = 0x70,
317 	static u8 mt352_clock_config [] = { 0x89, 0x38, 0x2d };  in advbt771_samsung_tdtc9251dh0_demod_init()
318 	static u8 mt352_reset [] = { 0x50, 0x80 };  in advbt771_samsung_tdtc9251dh0_demod_init()
319 	static u8 mt352_adc_ctl_1_cfg [] = { 0x8E, 0x40 };  in advbt771_samsung_tdtc9251dh0_demod_init()
320 	static u8 mt352_agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,  in advbt771_samsung_tdtc9251dh0_demod_init()
321 				       0x00, 0xFF, 0x00, 0x40, 0x40 };  in advbt771_samsung_tdtc9251dh0_demod_init()
322 	static u8 mt352_av771_extra[] = { 0xB5, 0x7A };  in advbt771_samsung_tdtc9251dh0_demod_init()
323 	static u8 mt352_capt_range_cfg[] = { 0x75, 0x32 };  in advbt771_samsung_tdtc9251dh0_demod_init()
335 	return 0;  in advbt771_samsung_tdtc9251dh0_demod_init()
342 	unsigned char bs = 0;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
343 	unsigned char cp = 0;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
350 		cp = 0xB4;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
352 		cp = 0xBC;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
354 		cp = 0xB4;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
356 		cp = 0xBC;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
358 		cp = 0xF4;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
360 		cp = 0xFC;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
362 		cp = 0xBC;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
364 		cp = 0xF4;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
366 		cp = 0xFC;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
369 		bs = 0x01;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
371 		bs = 0x01;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
373 		bs = 0x02;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
375 		bs = 0x02;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
377 		bs = 0x02;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
379 		bs = 0x02;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
381 		bs = 0x08;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
383 	pllbuf[0] = 0x61;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
385 	pllbuf[2] = div & 0xff;  in advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
393 	.demod_address = 0x0f,
398 	.demod_address = 0x55,
411 	bttv_write_gpio(bt->bttv_nr, 0x0002, mode);   /* Reset */  in or51211_setmode()
420 	 * reset is controlled by GPIO-0  in or51211_reset()
421 	 * when set to 0 causes reset and when to 1 for normal op  in or51211_reset()
426 	 * reset set to 0 so if reloaded we have been reset.  in or51211_reset()
429 	int ret = bttv_gpio_enable(bt->bttv_nr, 0x001F, 0x001F);  in or51211_reset()
430 	if (ret != 0)  in or51211_reset()
432 	bttv_write_gpio(bt->bttv_nr, 0x001F, 0x0000);   /* Reset */  in or51211_reset()
435 	bttv_write_gpio(bt->bttv_nr, 0x0001F, 0x0001);  in or51211_reset()
443 	bttv_write_gpio(bt->bttv_nr, 0x0001, 0x0000);  in or51211_sleep()
447 	.demod_address = 0x15,
460 	struct i2c_msg msg = { .addr = 0x60, .flags = 0, .buf = buf, .len = sizeof(buf) };  in vp3021_alps_tded4_tuner_set_params()
464 	buf[0] = (div >> 8) & 0x7F;  in vp3021_alps_tded4_tuner_set_params()
465 	buf[1] = div & 0xFF;  in vp3021_alps_tded4_tuner_set_params()
466 	buf[2] = 0x85;  in vp3021_alps_tded4_tuner_set_params()
468 		buf[3] = 0x01;  in vp3021_alps_tded4_tuner_set_params()
470 		buf[3] = 0x02;  in vp3021_alps_tded4_tuner_set_params()
472 		buf[3] = 0x0C;  in vp3021_alps_tded4_tuner_set_params()
474 		buf[3] = 0x8C;  in vp3021_alps_tded4_tuner_set_params()
481 	return 0;  in vp3021_alps_tded4_tuner_set_params()
485 	.demod_address = 0x0a,
491 	static u8 mt352_clock_config [] = { 0x89, 0x38, 0x2d };  in digitv_alps_tded4_demod_init()
492 	static u8 mt352_reset [] = { 0x50, 0x80 };  in digitv_alps_tded4_demod_init()
493 	static u8 mt352_adc_ctl_1_cfg [] = { 0x8E, 0x40 };  in digitv_alps_tded4_demod_init()
494 	static u8 mt352_agc_cfg [] = { 0x67, 0x20, 0xa0 };  in digitv_alps_tded4_demod_init()
495 	static u8 mt352_capt_range_cfg[] = { 0x75, 0x32 };  in digitv_alps_tded4_demod_init()
504 	return 0;  in digitv_alps_tded4_demod_init()
517 	pllbuf[0] = 0x61;  in digitv_alps_tded4_tuner_calc_regs()
518 	pllbuf[1] = (div >> 8) & 0x7F;  in digitv_alps_tded4_tuner_calc_regs()
519 	pllbuf[2] = div & 0xFF;  in digitv_alps_tded4_tuner_calc_regs()
520 	pllbuf[3] = 0x85;  in digitv_alps_tded4_tuner_calc_regs()
525 		pllbuf[4] = 0x02;  in digitv_alps_tded4_tuner_calc_regs()
527 		pllbuf[4] = 0x88;  in digitv_alps_tded4_tuner_calc_regs()
529 		pllbuf[4] = 0x08;  in digitv_alps_tded4_tuner_calc_regs()
532 		pllbuf[4] |= 0x04;  in digitv_alps_tded4_tuner_calc_regs()
546 	int ret = bttv_gpio_enable(bt->bttv_nr, 0x08, 0x08);  in digitv_alps_tded4_reset()
547 	if (ret != 0)  in digitv_alps_tded4_reset()
552 	bttv_write_gpio(bt->bttv_nr, 0x08, 0x08); /* High */  in digitv_alps_tded4_reset()
553 	bttv_write_gpio(bt->bttv_nr, 0x08, 0x00); /* Low  */  in digitv_alps_tded4_reset()
556 	bttv_write_gpio(bt->bttv_nr, 0x08, 0x08); /* High */  in digitv_alps_tded4_reset()
560 	.demod_address = 0x0a,
566 	.serial_mpeg      = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
574 	bttv_write_gpio(bt->bttv_nr, 0x00e00007, 0x00000001); /* High */  in lgdt330x_reset()
575 	bttv_write_gpio(bt->bttv_nr, 0x00e00007, 0x00000000); /* Low  */  in lgdt330x_reset()
578 	bttv_write_gpio(bt->bttv_nr, 0x00e00007, 0x00000001); /* High */  in lgdt330x_reset()
604 				      0x0e, card->i2c_adapter);  in frontend_init()
607 				   card->i2c_adapter, 0x61,  in frontend_init()
692 				   card->i2c_adapter, 0x61,  in frontend_init()
718 	if (result < 0) {  in dvb_bt8xx_load_card()
726 	memset(&card->demux, 0, sizeof(struct dvb_demux));  in dvb_bt8xx_load_card()
738 	if (result < 0) {  in dvb_bt8xx_load_card()
745 	card->dmxdev.capabilities = 0;  in dvb_bt8xx_load_card()
748 	if (result < 0) {  in dvb_bt8xx_load_card()
756 	if (result < 0) {  in dvb_bt8xx_load_card()
764 	if (result < 0) {  in dvb_bt8xx_load_card()
770 	if (result < 0) {  in dvb_bt8xx_load_card()
776 	if (result < 0) {  in dvb_bt8xx_load_card()
785 	return 0;  in dvb_bt8xx_load_card()
819 		card->gpio_mode = 0x0400c060;  in dvb_bt8xx_probe()
820 		/* should be: BT878_A_GAIN=0,BT878_A_PWRDN,BT878_DA_DPM,BT878_DA_SBR,  in dvb_bt8xx_probe()
827 		card->gpio_mode = 0x0400C060;  in dvb_bt8xx_probe()
836 		card->gpio_mode = 0x0400c060;  in dvb_bt8xx_probe()
849 	case BTTV_BOARD_AVDVBT_771: //case 0x07711461:  in dvb_bt8xx_probe()
850 		card->gpio_mode = 0x0400402B;  in dvb_bt8xx_probe()
853 		/* A_PWRDN DA_SBR  DA_APP[0] PKTP=10 RISC_ENABLE FIFO_ENABLE*/  in dvb_bt8xx_probe()
857 		card->gpio_mode = 0x2204f2c;  in dvb_bt8xx_probe()
862 		 * 0x33 = 5,4,1,0  in dvb_bt8xx_probe()
865 		 * IOM = 0 == audio A/D  in dvb_bt8xx_probe()
866 		 * DPM = 0 == digital audio mode  in dvb_bt8xx_probe()
868 		 * then 0x33 (13 is set by start_capture)  in dvb_bt8xx_probe()
875 		card->gpio_mode = 0x0100EC7B;  in dvb_bt8xx_probe()
911 	return 0;  in dvb_bt8xx_probe()